Principal DFT Engineer

Job description

We are looking for an experienced DFT Lead to own end-to-end Design-for-Test activities for complex Automotive MCU/SoC products . The role will drive DFT architecture, implementation, verification, and production-test readiness while working closely with SoC Design, Verification, PTE, Product and Test Engineering teams.

Key Responsibilities

Own the DFT architecture and strategy for automotive MCU/SoC products from specification through silicon production readiness. Define and implement DFT solutions including scan architecture, compression, memory BIST, logic BIST, boundary scan/JTAG and test access architecture , as applicable. Drive DFT implementation and associated RTL/design updates , working closely with SoC, IP and RTL design teams. Own DFT verification and simulation , including test-mode validation, scan/MBIST connectivity, ATPG-related simulations and gate-level verification.

Drive ATPG and pattern generation , validation and release of production-ready test patterns to Product and Test Engineering teams. Act as the primary technical interface with PTE/Product/Test teams for DFT, test-pattern and silicon-test requirements. Work with design teams to define and align DFT requirements, test modes, clocks, resets, power domains, constraints and chip-level integration requirements . Review DFT coverage, pattern count, test time and testability metrics, and drive closure of coverage gaps.

Support silicon bring-up, pattern debug, test failures and yield-related DFT investigations . Own DFT deliverables, reviews, sign-off criteria and milestone tracking across the product development lifecycle. Identify DFT-related technical and schedule risks early and drive cross-functional closure.

Qualifications

Required Skills & Experience

15+ year experience in DFT architecture and implementation for complex MCU/SoC devices . Hands-on expertise in scan insertion, scan compression, ATPG, MBIST and JTAG/boundary scan . Strong understanding of RTL and gate-level design, clocks, resets, power domains and SoC integration. Experience with DFT simulation, pattern verification and gate-level simulation/debug . Experience in ATPG pattern generation, fault coverage analysis and production pattern delivery.

Good understanding of the interface between design DFT and ATE/production testing . Experience working with Product Engineering and Test Engineering teams during silicon bring-up and production ramp. Familiarity with industry-standard DFT tool flows from Siemens EDA, Synopsys and/or Cadence . Strong problem-solving and debugging skills with the ability to drive issues across multiple engineering organizations. Ability to independently lead DFT activities and communicate effectively with architecture, design, verification, physical design and product/test teams.

Preferred Experience

Experience with automotive MCU or automotive SoC development . Exposure to ISO 26262 / functional safety requirements and their impact on test architecture. Experience with advanced DFT methodologies such as hierarchical test, embedded compression, logic BIST, repair/redundancy schemes or safety-oriented test features. Understanding of production test cost, test time, coverage, diagnostic requirements and yield considerations.

What We Are Looking For

We are looking for someone who can take technical ownership of DFT , not just execute an established flow. The ideal candidate can make architecture decisions, work hands-on through implementation and verification, anticipate downstream production-test requirements, and effectively connect the design organization with Product and Test Engineering .