Staff/ Sr Staff Engineer, Physical Design

Job description

Experience

7-10 years

Role Summary

We are seeking an experienced Physical Design Engineer with strong debug skills in Synthesis, UPF, VCLP, LEC to join our semiconductor backend team. The role focuses on RTL synthesis ownership, LEC closure, UPF development, and VCLP sign‑off for complex SoC designs, working closely with Physical Design, DFT, and Front‑End teams.

Key Responsibilities

Own RTL synthesis from elaboration to final sign‑off. Develop and debug design constraints and support DFT insertion. Understand Physical design cycle and different handshaking across teams. Perform and close logic equivalence checks (LEC) across RTL, synthesized, and ECO netlists. Create, maintain, and debug UPF, ensuring alignment with FE power intent. Define and manage power domains (power switches, isolation, retention, always‑on).

Support low‑power sign‑off (VCLP / power checks). Handle RTL ECOs during late design stages. Automate flows using TCL scripting.

Qualifications

Required Qualifications

4+ years of hands‑on experience in Physical design for SoC designs. Strong knowledge of RTL, synthesis optimization, and low‑power design. Hands‑on experience with UPF creation and power‑domain modelling. Experience with tools such as Cadence Genus, Synopsys Fusion Compiler, Conformal, VCLP. Strong TCL scripting skills (Perl/Python is a plus). Preferred Advanced node experience (7nm / 5nm or below). Power‑aware ECO experience.

Exposure to physical‑aware synthesis. Ownership of subsystem or SoC‑level UPF.