Staff Package Design Engineer

Job description

Job Summary

We are actively advancing technological innovation in the semiconductor package assembly, with a focus on next generation packaging technologies such as PowerQFN, Flip-Chip, and SiP. In particular, the fields of AI, High Performance Computing (HPC), and Vertical Power Delivery (VPD) are rapidly increasing their demand for higher density, higher reliability, and high thermal dissipation package technologies. This role offers the opportunity to work on cutting edge technologies — such as power packages for AI/HPC, VPD, Server VR core/peripheral, and Accelerator/GPU markets — and contribute to the development of packaging technologies that underpin innovations shaping society, including AI and next generation mobile computing.

Key Responsibilities

Design and develop package and interconnect methods for Renesas’s packaging needs in the areas of Power SiP/modules, flip-chip LGA, multi-chip module and power device packaging Work with OSAT/CM to develop, run DOEs to optimize processes and establish process specifications. Work with Product Groups and Reliability teams to qualify new packages and processes within required time frame. Ensure smooth transition into production by resolving all process integration issues, establishing production controls and monitors, and monitoring / resolving process issues.

Develop and maintain technical expertise on advances and innovations in advanced leadframe, power SiP/modules, and flip chip interconnects. Address internal and external customer complaints working with peers of Marketing, Product groups, Quality and Operations organization to satisfy growth in businesses.

Qualifications

Masters / Bachelor’s degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering. 5-15 years of relevant experience in package development emphasizing leadframe, laminate, power QFN/SiP/module, flip-chip packaging, and wafer Front-Side (FSM) / Back-Side (BM) Metallization processing. Understanding of semiconductor power device package assembly processes, materials and technology. Knowledge of AutoCAD, Excel, PowerPoint, Word.

Knowledge of wafer front-side / backside metallization, wire-bonding, flip chip, multi-chip module, SPC (Statistical Process Control) and statistical analysis. Strong interpersonal and communication skills. Strong analytical and presentation skills.