Staff Engineer, STA and Synthesis

Job description

The STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. This role owns timing constraint development and validation, performs detailed setup/hold and variation-aware analysis, and partners closely with Synthesis, CTS, Physical Design, and Design teams to debug violations and drive ECO-based optimizations through tapeout.

Responsibilities

Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners. Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations. Work closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure. Develop and maintain timing constraints including SDC creation, validation, and signoff readiness. Drive timing closure through ECO implementation and timing optimization.

Analyze timing impact due to process, voltage, and temperature variations. Support timing signoff for pre-layout and post-layout stages. Perform cross-functional reviews for timing convergence and provide recommendations. Generate timing reports and communicate closure status to project stakeholders.

Qualifications

7–10 years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs. Strong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow. Hands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts. Good understanding of clock tree, clock uncertainty, latency, skew, and jitter. Experience in timing constraints development and debugging.

Strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis. Familiarity with timing closure techniques and ECO methodologies. Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus. Good scripting skills in Tcl, Perl, or Python. Ability to analyze and resolve timing violations independently. Nice to have Exposure to low-power timing analysis and UPF/CPF-aware STA.

Familiarity with SI-aware timing, Crosstalk analysis, and IR-drop-aware timing closure. Knowledge of advanced technology nodes and variation-aware signoff methodologies. Exposure to automation and flow development. Experience in cross-functional collaboration with PD, RTL, and Signoff teams.