雲端伺服器Cpld/Fpga/HW開發設計

Job description

工作說明

• Develop CPLD for Server application and basic power sequence control.
• Proprietary design for system requirement through CPLD/ HDL development.
• Develop FPGA for Server application.
• Design and develop FPGA/CPLD digital logic using Verilog/SystemVerilog.
• Implement FPGA/CPLD system-level simulation, functional simulation, and verification.
• Work closely with EE engineers to integrate FPGA/CPLD into system architectures and troubleshoot issues.
• Develop automation tools and build automated testing environment. 資格需求
• With bachelor’s degree of Electronics, EE, or CS.
• With 3+ years HDL coding experience (Preferable to Verilog).
• Possess basic knowledge of Digital Circuit Design ( Combinational Logic, Sequential Logic, FSM, etc).

Familiar with PC industry standards

• SPI, I2C, USB, SGPIO, etc.
• Familiar with UVM to verify FPGA/ ASIC.
• Familiar with C, C++, or Python.
• Familiar with board level design is a plus.
• With good English competency in 4 skills, Toeic 600+.