OpenNash Jobs
Western Digital · San Jose, CA

Principal RFIC Design Engineer

San Jose, CA, United StatesFull-timeSenior individual contributorDesign

Listed on Western Digital’s official careers site. Posted October 14, 2026. Check that it is still open and apply there.

Apply on Western Digital’s careers site →

Job description

ESSENTIAL DUTIES

AND RESPONSIBILITIES: Designer will be responsible for the design of high performance analog and mixed-signal circuit blocks. Responsibilities include transistor level, block level and module level circuit architecture, design, simulation, optimization, layout supervision, layout verification, preparation of test plan for the test group, product characterization, reliability and yield assessment and modeling, simulation to bench and bench to test correlation, bench evaluation both at silicon level and at applications level, and documentation.

Job responsibilities require ability to communicate at all levels and with cross functional groups. Candidate must have good verbal and written communications skills and demonstrated track record of circuit innovation, must be a team player, be adaptable, and accept constructive criticism

Qualifications

Must have hands-on design and development experience in analog and mixed-signal integrated circuit Must have experience in at least one preferably multiple area of full CMOS circuit design and development in: Amplifiers – operational, instrumentation, wide-bandwidth etc. PMIC – Linear and switched regulators, Low-drop out regulators etc.

Data converters – ADC, DAC, Flash and SAR type

  • Must have experience in 40nm and below CMOS technology
  • Must have a demonstrable track record of successful design releases and mass production
  • Must have thorough knowledge of industry standard EDA tools (Cadence, Mentor, Siemens, Ansys etc.) Experience with analog layout techniques of mismatch reduction, gradient suppression, parasitic effects minimization Experience with floor planning, block level routing and top level chip routing
  • Knowledge of high performance and deep CMOS analog reliability considerations such as EM-IR, SOA and VDR and relevant mitigation techniques Functional knowledge of logic digital circuits and understanding of basic digital design flow Experience working with distributed design teams a plus
  • Must possess strong written and verbal communication skills BSEE with minimum
  • 10+ years of experience MSEE with minimum
  • 8+ years of experience PhD with minimum
  • 4+ years of experience

More jobs at Western Digital

Organization Effectiveness & Design Lead

San Jose, CA, United States

Associate, Corporate Development Analyst

San Jose, CA, United States

Associate, Corporate Strategy Analyst

San Jose, CA, United States

Similar jobs at other companies

Principal Engineer- Design

ON Semiconductor · San Jose, CA, United States

Principal Design Verification Engineer

Renesas Electronics · San Jose, CA, United States

RFIC Design Engineer

Qualcomm · San Diego, California, United States of America

Senior RFIC Design Engineer

Qualcomm · Santa Clara, California, United States of America

Circuit Design Engineer, Principal

Lockheed Martin · Goleta, CA

OpenNash lists jobs from employers’ own careers sites and does not handle applications. Dates come from the employer where stated; “first seen” and “last checked” are our own observations.