Lead SOC DFT Engineer

Job description

Define testability. Deliver quality. We are looking for a Senior SoC DFT Engineer with 4-5 years of experience to join our Connectivity team within the Embedded Processing Division. You will be responsible for implementing and validating DFT strategies throughout the product development cycle, ensuring the testability and quality of our semiconductor designs. You'll work alongside a team of enthusiastic DFT engineers, apply your expertise and deliver robust and reliable products.

Qualifications

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Around 4-5 years of experience in DFT, with focus on digital and mixed signal designs. Strong proficiency in DFT tools like Cadence Modus, Genus, etc. Experience with ATPG, scan insertion and test pattern generation for high complexity designs. Hands-on experience with DFT-related EDA tools and methodologies, including scan compression, boundary scan, memory BIST, JTAG, etc.

Familiarity with silicon bring-up and post-silicon debug is desirable. Strong knowledge of DFT techniques, methodologies, and industry standards, such as IEEE 1149.1. Experience in scripting languages, such as Perl or Python, for automation and data analysis is desirable. Strong analytical and problem-solving skills, with the ability to identify and address DFT-related issues and challenges.