Digital Design Engineer

Job description

Job Title

RTL Digital Design Engineer We are looking for a passionate RTL Design Engineer with 3–5 years of hands-on experience in digital design for ASICs or SoCs. The candidate will work on cutting-edge semiconductor designs from specification to tape-out, collaborating with cross-functional teams including architecture, verification, and physical design.

Key Responsibilities

RTL Coding and microarchitecture : Design and implementation of digital logic at the RTL level using Verilog, VHDL, System verilog. Collaborate with system architects and other cross functional teams to ensure efficient design implementation and its verification. Optimize designs for performance, area, and power targets Contribute to system architecture.

Problem Solving and Quality

Participate in pre-silicon and post-silicon debug. Contribute to design reviews and improvements. Work closely with verification engineers to define test plans. Coordinate with physical design teams for timing closure and synthesis constraints.

Qualifications

Minimum Requirements

Experience : 3 to 5 years Experience with RTL Coding and microarchitecture Design and implementation of digital logic at the RTL level using Verilog, VHDL, System Verilog Experience in Verilog, VHDL, System Verilog. Experience with System-on-Chip (SoC) architectures specifically with ARM cortex-M cores and AMBA protocols (AHB and APB).

Preferred Skills and Experience

Proficiency in Verilog, VHDL, System Verilog. Strong understanding of digital logic design principles, including finite state machines, combinational and sequential circuits. Understanding of power saving methodologies, lint, CDC, synthesis processes, timing constraints and analysis, DFT. Familiarity with verification techniques and tools. Strong written and verbal communication skills.