UCIe Applications Engineer, Staff

Job description

We Are

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are

You are a seasoned engineering professional with a deep passion for advancing semiconductor technology. With at least a decade of experience in ASIC design, verification, or applications engineering, you bring a robust understanding of both front-end and back-end development. Your expertise extends to integrating cutting-edge Interface IP (IIP) within complex SoC environments, and you thrive on collaborating with customers to solve intricate technical challenges.

Your background is rooted in electrical engineering, computer engineering, or computer science, and you have a proven track record of working with advanced technology nodes such as 10nm, 7nm, 5nm, or 3nm. Your methodical approach, attention to detail, and high degree of self-motivation set you apart. You communicate complex ideas with clarity, whether you’re leading a customer workshop, participating in a technical review, or contributing application notes for the broader engineering community.

You are excited by the prospect of supporting the integration of Synopsys’ industry-leading UCIe (Universal Chiplet Interconnect Express) IP into next-generation products. You are comfortable navigating the latest EDA tools, supporting both simulation and silicon bring-up phases, and you’re eager to provide hands-on guidance at every stage of the SoC development lifecycle. You value inclusion and diversity, and bring a collaborative spirit to every team you join, believing that the best solutions emerge from diverse perspectives and experiences.

What You’ll Be Doing

Guiding customers through the integration of Synopsys UCIe IP into their ASIC SoC and systems, addressing both technical and process challenges. Providing expert advice on IIP configuration, simulation, synthesis, floorplanning, static timing analysis (STA), and design-for-test (DFT) strategies. Conducting in-depth integration reviews at key SoC development milestones to ensure optimal IP performance and compatibility.

Delivering comprehensive training and workshops to customer engineering teams on the latest UCIe specifications and integration best practices. Collaborating with Synopsys R&D to develop application notes and technical collateral on advanced integration topics. Providing feedback and insights to R&D for continuous improvement of Synopsys IIP products based on customer experiences and emerging industry trends. Participating in internal design reviews to align product development with evolving customer needs and market demands.

The Impact You Will Have

Accelerating customer success by ensuring seamless integration of Synopsys UCIe IP, reducing time-to-market for innovative SoC solutions. Enhancing the reliability and performance of next-generation semiconductor products across diverse market segments. Driving adoption of the latest chiplet interconnect standards through effective customer education and support. Contributing to the evolution of Synopsys’ IP portfolio by relaying critical customer feedback and identifying opportunities for product enhancement.

Influencing the direction of industry standards and best practices through thought leadership and technical collaboration. Representing Synopsys at industry events, reinforcing our leadership position in IP integration and semiconductor innovation. Building long-term partnerships with key customers, fostering trust and collaboration across the semiconductor ecosystem.

What You’ll Need

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Minimum 5 years of experience in ASIC/Analog PHY design, or applications engineering within advanced technology nodes (10nm/7nm/5nm/3nm). Hands-on expertise in mixed-signal and high-speed interface design and integration, ASIC front-end and/or back-end implementation, including simulation, synthesis, floorplanning, and DFT.

Strong knowledge of EDA tools and methodologies, with additional experience in P&R, Physical Verification, and Signal/Power Integrity highly valued. Proven ability to debug and troubleshoot silicon and/or FPGA/hardware, with familiarity in Die-to-Die and PCIe/CXL protocols considered a significant advantage.

Who You Are

Detail-oriented, self-motivated, and committed to delivering high-quality results. Exceptional problem-solving and analytical skills, with a methodical approach to complex challenges. Excellent verbal and written communication skills, able to convey technical concepts clearly to diverse audiences. Collaborative team player who thrives in cross-functional environments and values diversity of thought. Adaptable and eager to continuously learn about new technologies and industry trends.