LPDDR PHY IP Verification Engineer

Job description

Our LPDDR PHY IP team is looking to add a Digital ASIC Verification Engineer to our team. In this role you will be responsible for developing test benches and verifying integrated IP Subsystems for our global customers.

Key Qualifications

BSEE in EE with 6+ years of relevant experience or MSEE with 3+ years of relevant experience Experience in ASIC RTL design and verification at the chip level and block level Strong Verilog, system Verilog, UVM, PERL, and TCL skills

• Knowledge in silicon debugging
• Demonstrates good communication skills in both

Mandarin and English

• Demonstrates good analysis and problem-solving skills
• Knowledge of high speed interface protocols is a plus