Analog Methodology Architect & AI Enthusiast - 19051

Job description

We Are

At Synopsys, our Silicon IP business is expanding to serve growing demand for special-purpose silicon. We are moving beyond traditional standards-based IP into application-optimized IP (AOIP), helping customers develop differentiated silicon tailored to specific workloads and system architectures. As AI drives demand for custom silicon across hyperscalers and system companies, we use our interface IP leadership, system expertise, and engineering scale to deliver optimized IP subsystems and platforms that accelerate time-to-market while improving performance and efficiency.

The acceleration of frontier intelligence is fueling an unprecedented demand for compute power while increasing system complexity, and purpose-built silicon is reshaping the IP market.

You Are

You are an experienced and passionate Analog Methodology Engineer with a deep understanding of mixed-signal circuit design principles and emerging AI/ML technologies. You thrive in a collaborative environment and work well with a cross-functional team of experts. Your hands-on experience with transistor-level simulation, reliability analysis, and static timing analysis (STA) sets you apart. You are proficient in scripting and automation, and you use those skills to streamline design processes and mentor other engineers.

You apply AI and machine learning to analog circuit optimization, your knowledge spans analog and mixed-signal circuits, and you have a strong background in silicon IP release requirements. You are also credible with customers, product teams, and foundries, and you can turn methodology strategy into decisions other organizations will adopt. Your communication is clear, and you are self-motivated, detail-oriented, and committed to excellence.

What You’ll Be Doing

The Analog Integration Team (AIT) exists to coordinate and accelerate methodology adoption across analog and adjacent engineering domains, including circuit-to-layout, circuit-to-timing, silicon-to-lab correlation, SI/PI integration, and other mixed-signal cross-domain workflows.

In this role, you will: Provide clear ownership for analog and adjacent-domain methodology areas. Act as the focal point for customer-driven methodology requirements and integration challenges. Be accountable for prioritization, adoption, stakeholder engagement, and execution. Improve coordination across product teams and adjacent engineering organizations, including engagement with customers and foundries. Support methodology for application-optimized IP and the special-purpose silicon customers are building for specific workloads and system architectures.

The Impact You Will Have

Establish sustainable ownership for analog and adjacent-domain methodologies. Improve responsiveness to customer methodology requirements. Reduce ambiguity on methodology ownership and escalation paths. Improve alignment between methodology strategy and execution. Accelerate methodology adoption for strategic initiatives and customers, including application-optimized IP for special-purpose silicon. Provide measurable accountability for methodology development, deployment, and customer engagement.

Who You Are

You have a Bachelor's degree in Electrical Engineering, Computer Engineering, or a similar technical field; MSEE or PhD preferred. You have 25-30 years of experience in IC design with a BSEE degree, or 22-25 years with an MSEE or PhD. You have expert knowledge of analog and adjacent-domain methodology, including circuit-to-layout, circuit-to-timing, silicon-to-lab correlation, SI/PI integration, and other mixed-signal cross-domain workflows.

You have a deep understanding of transistor-level circuit design, CMOS fundamentals, and physical IP, including reliability effects such as electromigration, IR drop, and aging. You have experience defining methodology for advanced nodes with circuit enablement teams and foundries. You have experience collaborating across a broad mixed-signal IP portfolio and aligning methodology requirements among multiple engineering organizations.

You set the objectives and approach for critical methodology assignments, and you coach, review, and approve the work of others. You take on unique issues that can determine success or shape future methodology, including cases where the important factors are not all explicit. You use independent judgment, and you lead the choice of methods, techniques, and evaluation criteria. You are the lead for major customers, and the main partner to circuit enablement and foundries on advanced-node methodology.

You influence decisions in ambiguous or sensitive situations. You are the contact for product teams’ leadership and the organizations that plan, enable, apply, and bring the IP to market. You also connect this work across the broader mixed-signal IP portfolio. You can represent it to executive leadership when the matter is strategically important. You own priorities, customer engagement, and execution strategy for analog and adjacent-domain methodologies.

The Team You’ll Be a Part Of

You will join the Analog Integration Team (AIT). AIT coordinates and accelerates methodology adoption across analog and adjacent engineering domains.

The team owns those methods end-to-end

customer requirements, integration challenges, prioritization, stakeholder engagement, and execution. You will work with product teams, adjacent engineering organizations, and directly with customers and foundries. The team’s job is to turn methodology strategy into accountable action and to help strategic IP programs adopt it faster.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Inclusive work culture supporting diverse backgrounds and experiences. Reasonable accommodations available throughout the recruitment and employment process.

For accommodation requests, contact [email protected] .