Sr Staff Engineer, Design Verification

Job description

This is a full-time, on-site role for a Senior Hardware Verification Engineer using UVM, located at Hyderabad, India The role involves developing and maintaining UVM-based verification environments, writing test benches, test cases, and coverage models for complex IP and SoC designs. The engineer will analyze specifications, define verification plans, create and execute verification scenarios, and debug RTL issues in close collaboration with design, architecture, and firmware teams.

Daily tasks include running regressions, monitoring coverage metrics, performing root-cause analysis of failures, and contributing to continuous improvement of verification methodologies and automation. The role may also include mentoring junior engineers, participating in design and verification reviews, and aligning verification activities with project schedules and quality standards.

Qualifications

Bachelor's or master's degree in Electronics Engineering, Electrical Engineering or a related discipline. 6 - 14 years of experience in Digital Verification with Strong expertise in System Verilog, UVM methodology and constrained-random verification. Experience with Formal Verification techniques and tools to complement simulation-based verification - advantage. Solid understanding of Computer Architecture, including memory hierarchies, bus protocols, and high-performance compute subsystems.

Proficiency with verification tools and flows (e.g., simulators, waveform viewers, coverage tools, regression management, scripting in Python/Perl/Tcl). Effective communication and collaboration skills, with the ability to work in cross-functional, multicultural teams. Experience in semiconductor product development for automotive, industrial, or embedded systems is an advantage Strong English, availability to support and cooperate with external teams including Business travels.

Experience using AI tools to accelerate code development, debugging, and improvement is an advantage.