Staff Verification Engineer

Job description

This is a full-time, on-site role for a Senior Hardware Verification Engineer using UVM, located in Israel Raanana The role involves developing and maintaining UVM-based verification environments, writing testbenches, test cases, and coverage models for complex IP and SoC designs. The engineer will analyze specifications, define verification plans, create and execute verification scenarios, and debug RTL issues in close collaboration with design, architecture, and firmware teams.

Daily tasks include running regressions, monitoring coverage metrics, performing root-cause analysis of failures, and contributing to continuous improvement of verification methodologies and automation. The role may also include mentoring junior engineers, participating in design and verification reviews, and aligning verification activities with project schedules and quality standards.

Qualifications

Strong expertise in Hardware Verification, including UVM methodology and constrained-random verification. Experience with Formal Verification techniques and tools to complement simulation-based verification. Solid understanding of Computer Architecture, including memory hierarchies, bus protocols, and high-performance compute subsystems. Background in Electrical Engineering or related field, with the ability to interpret circuit-level and system-level specifications.

Hands-on experience with RTL Design, including Verilog/SystemVerilog coding, synthesis considerations, and design-for-verification best practices. Proficiency with verification tools and flows (e.g., simulators, waveform viewers, coverage tools, regression management, scripting in Python/Perl/Tcl). Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline. Effective communication and collaboration skills, with the ability to work in cross-functional, multicultural teams.

Experience in semiconductor product development for automotive, industrial, or embedded systems is an advantage