Senior Staff Applications Engineer

Job description

As a Senior Staff Application Engineer for the Renesas Performance Computing Power Emulation Engineering team, you will be part of a fast-paced power management team supporting pre-silicon new feature bring-up and tapeout validation for AI and cloud infrastructure products. You will engage cross-functionally with IC design, firmware engineering, power systems architects, and systems engineering teams to deliver the most innovative power solutions.

Responsibilities

A broad comprehension of DC/DC power conversion is required, including familiarity with digital multiphase PWM controllers. Experience with high-speed digital interfaces is also required.

Key responsibilities include: Design multiphase power solutions for CPU/GPU/ASIC-class loads using digital multiphase controllers and Smart Power Stages. Design boards and power systems that interface with pre-silicon emulation of digital PWM controllers and power stages, enabling system-level validation ahead of silicon. Develop EVBs, including schematic capture, component selection, and thermal design. Oversee PCB layout for CPU/GPU-class boards to meet power delivery requirements, including current density, copper allocation, sensing, PDN, and thermal performance.

Design and review high-speed digital routing, including differential clock and data pairs with controlled impedance and high-speed single-ended signals, managing crosstalk, reflections, and EMI. Validate power performance in the lab (load transient, efficiency, sequencing, protection, telemetry) and signal quality using oscilloscopes, VNAs, and TDRs. Support pre-silicon new feature bring-up and tapeout validation, working with IC design, firmware engineering, and power systems architects to debug and close issues.

Qualifications

Bachelor's or Master's degree in Electrical Engineering or related field. 10+ years of relevant experience in power design for CPU/GPU/ASIC-class loads, including multiphase DC/DC converters and digital power management products, with strong emphasis on board-level design and validation. Experience with high-speed differential clock and data interfaces (SerDes-class) and high-speed single-ended routing (such as DDR), including channel modeling, jitter/crosstalk analysis, eye diagrams, and compliance/margining.

Strong lab skills with high-bandwidth instruments (scopes, VNAs, TDRs), power validation equipment, measurement-simulation correlation, fixture/probing design, and de-embedding. Demonstrated leadership in cross-functional design reviews, architectural influence, and clear communication of power and SI/PI concepts to diverse audiences

Preferred Qualifications

Hands-on experience with leading SI/PI/EM tools (e.g., Ansys HFSS 3D/Layout, SIwave, Clarity, CST, Keysight ADS Momentum/Sigrity, HSPICE, HyperLynx). Experience designing boards that interface with pre-silicon emulation platforms. Track record of bringing complex high-speed hardware from concept to production, including multiple design spins and volume manufacturing support. Experience with AVSBUS, SVID, SVI3, and PWM VID control bus architectures.

Experience with high-speed differential clock and data interfaces such as PCIe, Ethernet, and USB, and high-speed single-ended interfaces such as DDR memory.

Key Skills and Tools Power Design

Digital multiphase VR design, Smart Power Stages, control loop theory, and PDN analysis.

Design Tools

Proficiency in schematic capture and ECAD layout tools (such as Altium, Cadence Allegro, or Mentor Graphics).

Analysis Software

Using simulation tools for electromagnetic and signal and power integrity analysis (such as Keysight PathWave or Ansys HFSS).

Lab Equipment

Hands-on operation of oscilloscopes, TDRs (Time-Domain Reflectometers), logic analyzers, and electronic loads.