High-Speed SerDes Interface Evaluation Leader

Job description

【Background of the Recruitment】 As automotive electrification and intelligence continue to advance, automotive SoCs have become a core technology that directly supports vehicle performance and functionality. The R-Car series has evolved as a large-scale automotive SoC through the advanced integration of a wide range of IPs, including CPU, high‑speed interfaces, memory, AI/video, functional safety, and security. Among these technologies, high‑speed SerDes interfaces such as PCIe and CSI and DP and UCIe play a critical role in overall system performance and reliability.

As interface speeds continue to increase and system complexity grows, ensuring quality through thorough silicon‑level evaluation and signal integrity verification has become increasingly important. In this context, we are seeking a technical leader who has hands‑on experience in high‑speed SerDes interface evaluation and can work closely with design teams and IP vendors to lead evaluation activities from a technical standpoint.

By taking ownership of evaluation and contributing technical judgment to development, this role is expected to play a key part in improving the overall quality of our automotive SoCs. 【Job Description】 Lead the technical execution of high‑speed SerDes interface evaluation for automotive SoCs (R-Car series), covering interfaces such as PCIe, CSI, DP, UCIe, SerDes PHY, and other high‑speed I/F as applicable. Drive evaluation activities including silicon/board-level testing, signal integrity/quality assessment, stress testing, and standards/compliance confirmation, ensuring interface quality and robustness.

Define and align evaluation strategy, organize test items, and consolidate evaluation results into actionable outputs for stakeholders. When issues occur, coordinate with design teams, SoC stakeholders, and IP vendors to perform triage, root-cause investigation, and countermeasure planning. Provide technical leadership to evaluation members across sites and functions, helping establish clear evaluation flow and decision criteria to improve overall execution quality ※The full details regarding your position scope as well as any future potential changes in work location and job scope will be provided during the interview process.

Qualifications

【MUST】 Hands‑on experience in evaluation or verification for high‑speed interfaces (e.g., SerDes, PCIe, UCIe). Experience in issue analysis, root‑cause investigation, and countermeasure discussion based on silicon/board evaluations, signal‑quality assessment, and stress testing. Ability to summarize results and conduct technical discussions and alignment with design teams and stakeholders. Knowledge/experience related to analog behavior and characteristics relevant to high‑speed links (e.g., PLL/PHY, jitter, noise, SI/PI).

Ability to collaborate technically in English with design sites in India and Vietnam, as well as IP vendors. 【WANT】 Experience leading or co‑leading evaluation for a specific high‑speed interface such as PCIe, CSI, DP, UCIe, or SerDes PHY. Experience with high‑speed measurement and analysis using tools such as oscilloscopes, BERT, and TDR. Experience coordinating with external IP vendors on technical inquiries, issue alignment, and evaluation result sharing.

Experience in automotive SoC evaluation or in products/projects with high quality and reliability requirements. Interest in expanding contribution beyond evaluation into broader cross‑functional collaboration with design and SoC teams. Japanese language proficiency at a conversational level