Sr Principal Engineer, NPU Architecture

Job description

Renesas is seeking a Sr Principal NPU Architect to define and lead the next generation of AI acceleration technologies for Automotive High Performance Compute (HPC) platforms. This role will be responsible for driving the architectural vision, hardware-software co-design strategy, and technical roadmap for Neural Processing Units (NPUs) deployed across future microcontroller (MCU), microprocessor (MPU), and heterogeneous compute platforms.

The successful candidate will combine deep expertise in AI accelerator architecture, system-level design, memory hierarchy, interconnect architecture, and performance optimization with a strong understanding of compiler technology and AI software frameworks. As a senior technical leader, this individual will influence long-term product strategy, guide investments in AI compute technologies, and collaborate across hardware, software, compiler, systems, and product teams to deliver industry-leading AI performance, efficiency, and scalability.

Responsibilities

AI and NPU Architecture Leadership Define the long-term architectural vision and roadmap for Renesas AI acceleration technologies. Lead the specification and development of next-generation NPU architectures targeting automotive inference, edge AI, generative AI, autonomous driving, and software-defined vehicle applications. Drive architectural decisions across tensor processing engines, vector processors, activation units, sparse computing architectures, and emerging AI compute paradigms.

Evaluate emerging AI hardware architectures, industry trends, and competitive products to influence future product direction. System Architecture and Hardware-Software Co-Design Define system-level architectures enabling efficient interaction between NPUs, CPUs, GPUs, DSPs, memory subsystems, and security domains. Partner with compiler, runtime, and AI software teams to optimize the complete AI execution stack. Drive NPU instruction set architecture (ISA), programming models, graph execution frameworks, and compiler-aware architectural features.

Ensure alignment between hardware architecture and emerging AI frameworks such as PyTorch, ONNX, TensorFlow, MLIR, and LLVM-based toolchains. Memory, Interconnect and Data Movement Optimization Architect high-bandwidth, low-latency memory hierarchies addressing modern AI workload requirements. Define cache architectures, scratchpad memory structures, DMA subsystems, data compression techniques, and memory management mechanisms.

Design scalable interconnect and Network-on-Chip (NoC) solutions utilizing AXI, ACE, CHI, and coherent fabric technologies. Optimize system bandwidth, latency, and power efficiency to maximize AI performance per watt. Performance Modeling and Architecture Exploration Develop and lead architecture modeling frameworks using C++, SystemC, TLM, or equivalent modeling environments. Conduct quantitative tradeoff analysis covering performance, area, power, scalability, safety, and cost.

Drive workload characterization and benchmarking using real-world AI applications including CNNs, Transformers, LLMs, vision workloads, and multimodal AI systems. Identify system bottlenecks and define architectural innovations to improve throughput, utilization, and efficiency. Functional Safety, Security and Virtualization Define automotive-grade architectures compliant with ISO 26262 and other relevant safety standards.

Architect virtualization, partitioning, and isolation technologies supporting software-defined vehicle platforms. Ensure security and safety requirements are incorporated into NPU architecture from concept through implementation. Enable multi-domain workload execution across safety-critical and non-safety-critical environments. Technical Leadership Act as the technical authority for NPU architecture within Renesas. Provide mentorship and guidance to architects, designers, performance engineers, and software teams.

Influence product strategy, technology investments, and external partnerships. Represent Renesas in technical discussions with customers, ecosystem partners, IP vendors, and industry forums.

Qualifications

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. PhD preferred.

Experience

15+ years of semiconductor architecture experience, including significant experience in AI accelerators, NPUs, GPUs, DSPs, or other high-performance compute architectures. Demonstrated ownership of architecture definition through silicon execution and product delivery. Proven track record leading cross-functional architecture initiatives spanning hardware and software domains.

Technical Expertise Deep knowledge of AI/ML workloads including

Convolutional Neural Networks (CNNs) Transformers Large Language Models (LLMs) Generative AI Computer Vision Multi-modal systems

• Strong understanding of: NPU architecture Computer architecture Memory hierarchy design Cache coherency Data movement optimization Hardware performance modeling Expertise with: AXI / ACE / CHI protocols NoC architectures SystemC/TLM C++ Performance simulation frameworks
• Familiarity with: LLVM MLIR ONNX TensorFlow PyTorch AI compiler technologies Preferred Experience developing automotive AI or ADAS computing platforms.

Experience with functional safety (ISO 26262) and safety-compliant architectures. Experience architecting systems used in NVIDIA, Qualcomm, Samsung, AMD, Arm, Intel, Tesla, Mobileye, Google, Amazon, or equivalent AI compute environments. Contributions to industry standards, patents, publications, or significant architectural innovations.