Senior Staff Digital Design Engineer

Job description

Job Purpose and Dimensions

Develop micro-architecture and front-end digital design deliverables from concept to silicon with minimal supervision Develop digital functional blocks for various power management ASICs Principal Accountabilities: Lead optimized digital blocks design meeting functional and low power constraints and ensure spec compliance. Must have experience of defining Digital/Analog boundaries and digital design scope for Power Management ICs/Analog intensive ICs.

Must have experience of defining the micro-architectures and sub-blocks for the ICs to ensure optimized Digital design, RTL design and Gate level netlist etc. Must be able to handle Clock Domain Crossing across multiple clock domains seamlessly and in a glitch free manner Should be able to lead/collaborate for Logic Synthesis, Formal verification, Power estimation and STA. Should have experience of OTP, MTP, Efuse read/writes, controller design and data bus handling, Register read/write, Trimming of Analog parts/functions, DFT architecture and integration.

• Should be an expert of one or more Power Chip Communication I/Ps and protocols e.g. I2C, PMBUS etc. Verification test planning, feature extraction and verification test case development. Must have done multiple silicon debugs, root cause analysis of issues, design to silicon correlation etc.
• Support DFT strategy and implementation. Interface with P & R for digital hand-off and post layout verification. Perform physical silicon device area and power evaluation where necessary. Produce high quality documentation for owned blocks.

Develop work-around solutions where necessary to overcome device errata including documentation.

Key Performance Measures

Micro-architecture, functional, test plan specification delivered according to project schedule RTL coding using Verilog/System Verilog First time right success rate Pro-actively taking ownership of responsibilities. Deliver work in the agreed timescales as set by program schedule for all assigned tasks.

Knowledge, Skills and Experience

Experience in Logic design /micro-architecture / RTL coding.

• Must have hands on experience with Power product design, synthesis and timing analysis for complex Digital Circuits. Experience in Verilog/System-Verilog is a must. Experience working in semiconductor ideally PMIC with focus on mixed signal integrated circuits
• Hands on experience developing block and top-level timing constraints for STA and P & R sign off Understanding of design constraints and synthesis scripts Work independently on straightforward tasks, with little direction from manager
• Ability to propose innovative solutions Results-oriented and able to deliver on-time under a tight schedule Cross cultural awareness and sensitivity Proactive attitude about own role and contribution to company goals Ability to work both independently and part of a team Excellent command of verbal and written English Concise and precise communication and interpersonal skills within multi-site and multi-cultural environment

Qualifications

Degree level qualification in Electronics Engineering Key Relationships

Design team, in particular TPL (Technical Project Leader) and digital leads/manager