Staff Design Verification Engineer

Job description

We are seeking an experienced Staff ASIC/SoC Verification Engineer to join our dynamic and fast‑paced engineering team. In this role, you will be responsible for ensuring the functional correctness, robustness, and overall quality of our cutting‑edge semiconductor and SoC designs. If you thrive in a collaborative environment and enjoy solving complex technical challenges, this opportunity is an excellent fit. #LI-RT1

Responsibilities

Responsibilities

Verification Planning and Execution : Develop and execute comprehensive verification plans. Close verification with coverage closure, ensuring high-quality results. Apply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions.

Testbench Development

Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages. Implement reusable Verification IP (VIP) components. Collaborate with third-party VIP providers.

Methodology and Flows

Demonstrate a solid understanding of ASIC design and verification methodologies. Apply object-oriented programming principles effectively. Implement constraint random verification methodology.

Technical Skills

Proficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI). Familiarity with industry standards (e.g., I2C/SPI). Experience with low-power verification using UPF (Unified Power Format) is a plus. Knowledge of formal verification techniques is advantageous.

Collaboration and Communication

Work effectively with internal teams and external customers. Strong written and verbal communication skills. Initiative, analytical problem-solving abilities, and adaptability within a diverse team environment.

Qualifications

Required Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 10 Years of experience in SoC/IP verification,. Strong expertise in SystemVerilog , UVM , and advanced verification methodologies. Hands-on experience with ARM-based SoC architectures , AMBA protocols (AXI/AHB/APB), and system-level interactions. Proven ability to build reusable, scalable testbench architectures . Solid understanding of test planning , coverage-driven verification, and verification metrics.

Experience with GLS , timing verification, and debug. Knowledge of power-aware verification (UPF/CPF). Strong scripting and automation skills (Python, Perl, Shell, Make, etc.). Exposure to AI/ML techniques applied to verification (e.g., intelligent stimulus generation, failure triage, coverage optimization). Excellent problem-solving, debugging, and communication skills. #LI-RT1