Senior Digital Design Engineer

Job description

Job Description

The Role We are looking to expand our team with a Senior Digital IC Design Engineer. You will help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex mixed-signal IPs like DACs, ADCs, PLL and wireless interface etc. Why Join Us We create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs.

You will be able to build up a career in a successful international company, and you can participate in interesting international projects. Responsibilities #LI-RT1

Responsibilities

What You’ll Do

Define architecture and participate in feasibility studies for new analog/mixed-signal IP components Drive design and verification of state-of-the-art CMOS and SOI designs which can be reused across different market segments.

• Lead small teams on sub-projects and contribute to SoC integration
• Propose innovative solutions to meet customer and product needs
• Collaborate on DFT strategies and document designs thoroughly
• Partner with test, product, and applications engineering to ensure successful production release Documentation: including architecture and circuit descriptions, testing procedures, and safety mechanisms. #LI-RT1

Qualifications

What You’ll Need

Minimum BS/MS in Electrical Engineering or related technical field +5 years in ultra-low-power digital design using Verilog/System Verilog Capacity to think at the system level and to operate as a technical leader Creativity, dynamism, reliability and team spirit Excellent English written and verbal communication skills What Else You May Bring Experience in some of the following areas is a plus: Knowledge Verilog-A or VHDL-AMS.

Experience with embedded CPUs (e.g.

ARM Cortex, DSP), AMBA bus protocols (AHB/APB) Experience in ADC, DAC, PLL, power management systems Programming in Python for automation and in C/C++ for embedded software

• Design intent (timing constraints/SDC, power intent/UPF)
• Design of accelerators and signal processing components RTL to GDS flow, including logic synthesis, place-and-route, STA, power analysis Advanced digital verification methodology (e.g.

UVM) Knowledge in Functional Safety #LI-RT1