Senior System Management Architect

Job description

Our Host Management Team focuses on the holistic system- and board-level management of next-generation data center infrastructure. We architect the production, provisioning, management, power, and reset flows that keep complex, multi-silicon platforms operating securely and reliably. We bridge the gap between high-level orchestration (like Redfish and out-of-band management) and low-level hardware execution. We are seeking a Senior System Management Architect to lead the management architecture for our advanced SmartNIC cards.

You will be the resident expert for SmartNIC system management, ensuring that NIC ASICs, Baseboard Management Controllers (BMCs), MCUs, CPUs, and CPLDs operate in perfect unison. You will own the lifecycle management specifications for SmartNIC platforms—from factory provisioning and day-one deployment to complex orchestrated reset flows and secure recovery. If you are someone who enjoys looking at a high-level system diagram and then immediately diving into the I2C/I3C bus topologies and PLDM command structures required to make it work, this role is for you.

What you'll be doing

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery and reset flows for SmartNIC cards. Crucially, you will ensure that these board-level architectural decisions perfectly align with and support overarching platform-level needs, orchestrating seamless coordination between the NIC ASIC, BMC, CPU, and peripheral components.

Security & Provisioning

Specify security provisioning flows including OTP fusing, secure boot enablement, attestation key injection, certificate chain management, RPMC key derivation, and PQC (Post-Quantum Cryptography) requirements. Define IPN-to-OPN transition and component locking procedures.

Protocol Implementation & Guidance

Specify the use of standard management protocols (MCTP, PLDM, SPDM, NC-SI) across internal board interfaces to achieve secure boot, firmware updates, and telemetry gathering.

Hardware/Software Intersect

Dive deep into device-level hardware and software behaviour. Define CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets) for multi-host and standalone SmartNIC environments.

Interface Management

Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership

Collaborate tightly with Production teams, Hardware and Firmware Engineering, NIC FW/Driver teams, and QA to translate your architectural specifications into implementable, testable realities.

Technical Documentation

Author rigorous technical specifications, test plans, and architectural design documents to guide both development and factory production.

What we need to see

Deep System-Level Perspective: Proven ability to understand complex computing or networking systems top-to-bottom, with a specific background in SmartNIC boards, chassis, or network tray architectures.

Device-Level Expertise

Hands-on experience debugging or architecting flows involving BMCs (e.g., OpenBMC), MCUs, CPUs, and complex networking ASICs.

Protocol Fluency

Strong working knowledge of modern platform management and security protocols, specifically MCTP, PLDM (Type 2, 5, etc.), SPDM, and NC-SI.

Hardware Interface Knowledge

Deep familiarity with board-level communication buses (I2C, I3C, SPI, USB) and system interconnects (PCIe architecture, including link states and reset mechanisms).

Analytical Documentation Skills

Exceptional ability to write clear, unambiguous technical specifications, state-machine descriptions, and sequence diagrams.

Experience

Level: Typically requires a BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, alongside 8+ years of relevant industry experience.

Ways to stand out from the crowd

Experience with Redfish API definitions and OOB network infrastructure. Familiarity with hardware root of trust (HRoT / eROT) concepts and secure boot architectures. Experience with PLDM firmware update bundle packaging and update agent implementation. Experience with production line tooling, factory provisioning, and manufacturing test flows.

Networking Experience

Background in general networking principles, SmartNIC data-plane and offload operations, or high-speed data center topologies.