Principal Silicon Engineer

Job description

• Take ownership and responsibility for our STA execution
• Develop, improve, and update our STA methodology; work closely with vendors to align our flows to industry practices, resolve tool issues, and improve overall execution and reliability of STA flows
• Take an active role in early-phase design planning with STA execution including full-chip repeater planning, timing budgeting, constraint development, and early analysis Define & drive to STA milestones across project phases; manage STA rollups, analysis & reporting, ECO generation flows, and guidance to block development
• Ensure a convergent STA process and drive STA closure through all phases including final signoff for tapeout
• Work across teams to identify and resolve boundary timing issues, fullchip STA bottlenecks, etc.

Give guidance for floorplan adjustments and address timing issues, constraints, etc.

• Bachelor's degree in computer engineering, electrical engineering, or related field
• 7+ years of physical design/STA experience Experience with Synopsys design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime)
• 10+ years of hands-on physical design experience with focus on STA execution and signoff Deep expertise in STA, timing constraints, ECO generation, and STA signoff procedures
• Proficiency in flow automation, scripting (TCL/Perl) & tool debug
• Ability to develop & maintain timing closure checklists, to track and report STA progress through all design phases, and successfully execute STA closure on schedule
• Demonstrated tapeout experience in TSMC 5nm process or below