Design Verification Engineer

Job description

Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom silicon components. Work with a team to write constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness. Develop Verification IP (VIP) components to verify home grown designs. Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments.

Define and implement functional coverage and drive coverage closure. Collaborate with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third-party vendor teams to ensure pre-and-post-Si testing is comprehensive. Develop scripts for verification and validation infrastructure. Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.

This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information.

To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field OR Master's Degree in

Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. 3+ years of pre-silicon System on Chip (SOC), chip level, subsystem or IP verification experience. 3+ years of experience with verification principles, object-oriented programming, test plan development, testbench creation, stimulus generation, UVM/Open

Verification Methodology (OVM), and coverage-based verification. 3+ years of experience in SystemVerilog, C/C++, and scripting languages such as Python, Ruby or Perl.

Demonstrated experience on one or more of the following: Coherency, Caches, Fabrics, Double Data Rate (DDR) controllers, Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Advanced eXtensible Interface(AXI)/Coherent Hub Interface(CHI) protocol bridges or other complex IP/blocks or subsystems. Experience with a full product cycle from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff.

Experience creating, maintaining, or integrating test benches, checkers and stimulus using System Verilog Test Bench (SVTB), Universal Verification Methodology (UVM), Formal Verification and/or C/C++. Experience in automating verification processes using Python or another scripting language.