ASIC Engineer, Implementation

Job description

Meta is building custom silicon to power the next generation of infrastructure that supports AI, augmented reality, and virtual reality at scale. As an ASIC Implementation Engineer on the Infrastructure Silicon team, you will own the physical implementation of complex custom ASICs from RTL to tape-out, working across synthesis, place-and-route, timing closure, and signoff. In this role, you will collaborate closely with design, architecture, and verification teams to deliver high-performance, power-efficient silicon that meets the demanding requirements of Meta's data center and compute infrastructure.

Responsibilities

• Lead physical implementation flows for custom ASICs including synthesis, floorplanning, place-and-route, clock tree synthesis, and timing closure
• Drive static timing analysis and timing signoff across multiple process corners and operating conditions for complex hierarchical designs
• Develop and maintain implementation scripts and methodologies to improve quality of results and reduce turnaround time across the design flow
• Collaborate with RTL designers and architects to identify and resolve timing, area, and power trade-offs early in the design cycle
• Perform power analysis and implement power optimization strategies including clock gating, multi-voltage domain implementation, and dynamic power reduction techniques
• Execute physical verification flows including DRC, LVS, and antenna checks, coordinating with foundry and design teams to achieve clean signoff
• Contribute to the development and continuous improvement of implementation infrastructure, including tool configuration, runsets, and automation frameworks
• Partner with package and board engineers to define and validate chip-level IO constraints, bump maps, and signal integrity requirements
• Provide technical guidance to peers on implementation methodology, tool usage, and design-for-manufacturability best practices
• Analyze and communicate implementation results, risks, and trade-offs to cross-functional stakeholders including architecture and program management teams

Qualifications

• 6+ years of experience in ASIC physical implementation including synthesis, place-and-route, and timing closure on production tape-outs Experience with static timing analysis and timing signoff using industry-standard EDA tools such as Synopsys PrimeTime, Cadence Tempus, or equivalent Experience with physical verification flows including DRC, LVS, and antenna correction in advanced process nodes (7nm or below) Experience scripting and automating implementation flows using Tcl, Python, or equivalent languages Experience with power analysis and low-power implementation techniques including multi-voltage domain design and power intent specification
• Knowledge of Timing/physical libraries, SRAM Memories Experience with Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools Experience with or knowledge of RTL coding using Verilog/SystemVerilog
• Knowledge of Low power design Experience with Power, Performance, Area Analysis and techniques for reducing power
• Knowledge of Clock Domain Crossing, Reset Domain Crossing, LEC Scripting and programming experience using Perl/Python, TCL, and Make Synthesis Background, Timing Constraints Development, Floorplanning and STA