ASIC Engineer, Design Verification

Job description

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing with superior capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption.

They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains.

Responsibilities

• Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
• Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• Track record of 'first-pass success' in ASIC (Application-Specific Integrated Circuit) development cycles
• 8+ years of hands-on experience in SystemVerilog/UVM (Universal Verification Methodology) and/or C/C++ based verification
• 8+ years of experience in IP/sub-system and/or SoC (System on Chip) level verification based on SystemVerilog UVM and OVM (Open Verification Methodology) based methodologies Experience in one or more of the following areas along with functional verification - System Verilog Assertions, Formal, Emulation Experience in EDA/Electronic Design Automation tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation Experience with verification of ARM/RISC-V based sub-systems or SoCs Experience with simulators and waveform debugging tools Experience in technically planning, executing and leading the verification of multiple complex Sub-Systems or SoC or from multi-chiplet Solutions from Architecture to Silicon
• 15+ years of hands-on experience in development of UVM based verification environments from scratch Experience working across and building relationships with cross-functional design, model and emulation teams Experience with IP or integration verification of high-speed interfaces like Ethernet, PCIe, DDR, HBM Experience in the Networking domain with in-depth experience working with AI Compute, High-Speed IO Interconnects, Die-to-Die Interconnects, Ethernet, 400G MAC, RDMA, RoCE, NIC, TSO, LRO, TimeSync protocols Experience with development of fully automated flows and scripts for data exploration, analysis and performance verification Experience with revision control systems like Mercurial(Hg), Git or SVN