Silicon Validation Engineer, Infra Silicon

Job description

Meta's Infrastructure Silicon organization is seeking a Silicon Validation Engineer to lead silicon validation efforts for custom-designed accelerators and infrastructure ASICs powering Meta's data center fleet. In this role, you will drive end-to-end validation strategy across the full silicon lifecycle — from pre-silicon planning and emulation-based verification through post-silicon bring-up, characterization, and fleet-scale deployment.

You will serve as a technical authority bridging silicon design, systems architecture, and production infrastructure, ensuring that Meta's custom silicon meets rigorous performance, reliability, and functional requirements at scale.

Responsibilities

• Define and own comprehensive validation strategies for custom infrastructure ASICs, spanning functional correctness, performance characterization, reliability stress testing, and power analysis across pre- and post-silicon phases
• Lead pre-silicon validation planning using simulation and emulation environments, authoring test plans that map to architectural specifications and cover corner cases across compute, memory, and I/O subsystems
• Drive post-silicon bring-up activities including board-level debug, firmware integration, and systematic root-cause analysis of silicon failures using lab instrumentation and diagnostic tooling
• Develop and maintain automated validation frameworks, silicon diagnostics, and performance analysis tools that scale from early lab environments to large-scale data center deployments
• Collaborate with ASIC design, architecture, and physical design teams to provide validation feedback that influences design-for-testability decisions and next-generation silicon architecture
• Establish and track silicon quality metrics, characterization data, and yield analysis to inform productization decisions and deployment readiness gates
• Partner with systems and firmware engineering teams to validate host-side integration, PCIe and fabric interconnects, thermal management, and power delivery across full-stack server configurations
• Identify systemic silicon failure modes observed in the production fleet and drive corrective actions through design errata documentation, firmware workarounds, or architectural improvements
• Mentor other engineers on validation methodology, debug techniques, and best practices for infrastructure silicon bring-up and characterization
• Contribute to long-term validation infrastructure roadmaps, defining tooling investments and methodology improvements that improve coverage and reduce time-to-production for future silicon generations

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 8+ years of experience in silicon validation, hardware systems engineering, or post-silicon bring-up for custom ASICs, SoCs, or accelerator designs
• 8+ years of experience with pre-silicon validation environments including RTL simulation, emulation platforms, or FPGA prototyping Experience with post-silicon debug methodologies including use of logic analyzers, oscilloscopes, JTAG, and protocol analyzers for PCIe, DDR, or high-speed serial interfaces Experience developing validation automation frameworks and diagnostic tooling using Python, C, or C++ Experience collaborating across ASIC design, architecture, firmware, and systems teams throughout the silicon development lifecycle Experience with data center infrastructure silicon including AI/ML accelerators, network ASICs, or storage controllers in large-scale fleet environments Experience defining design-for-testability requirements and contributing to silicon architecture reviews from a validation perspective
• Familiarity with server systems architecture including PCIe topology, memory subsystems, and BMC-based platform management Experience with power and thermal characterization, reliability stress testing, and silicon yield analysis for productization