Engineering Manager, ML Compilers (Triton / Kernel DSLs)

Job description

As a Software Engineering Manager in the MTIA Software team, you will lead the development of Meta's ML compiler stack for custom AI accelerators — the layer that enables kernels, both hand-written and generated, run efficiently on MTIA silicon. Your team defines how Triton and lower-level DSLs map onto MTIA hardware, shaping language extensions, target-specific optimizations, and the kernel authoring experience used by kernel engineers, product groups, and model teams across Meta.

The work spans open-source contributions and internal compiler development, directly influences ISA and architecture roadmap decisions, and carries top-level executive visibility as a key AI infrastructure initiative. The team culture celebrates deep technical contributions with extensive knowledge-sharing, including external conference talks and published research.

Responsibilities

You will drive the development of the DSL compiler toolchain, including ML compiler integration, GEMM and non-GEMM kernel enablement, collectives support, and next-generation low-level DSLs. You will lead teams of engineers and technical leaders delivering large-scale projects across compiler infrastructure, kernel libraries, and production deployment on multiple accelerator generations You will stay technically engaged, contributing hands-on through AI tools to evaluate the technical direction and quality across your teams.

You will form trusted cross-functional partnerships with hardware/architecture, kernel, runtime, framework, and model teams while actively shaping strategy and roadmap, and you will balance near-term deployment commitments against long-term compiler investments. You will build and mentor engineers into AI-era leaders while maintaining high engineering craft standards

Qualifications

• 5+ years of experience in managing a software team in a fast-paced capacity Experience with compiler architecture and development, particularly with ML compilers or domain-specific languages (DSLs)
• Proven understanding and experience in executing full product life-cycles (prototyping, deployment, and support) Experience working closely with hardware architectures such as SIMD, GPU, RISC-V, AI accelerators, and influencing architecture roadmaps Experience with Triton, MLIR, or LLVM compiler infrastructure Experience with open-source community engagement and upstream contributions
• Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements) Experience with PyTorch compiler stack internals such as Inductor
• Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies Experience with different programming models for high-performance computations, e.g., GPU CUDA programming or OpenCL or OpenMP programming Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews) Experience with kernel-level performance optimization for AI accelerators