Hardware Engineer, Principal

Job description

Principal Verification Engineer Job Description

Independently architect UVM based verification environments including drivers, monitors, scoreboards, functional checkers, functional coverage. Innovative in functional coverage techniques and stress verification with testing all corners of DV – Passing/Failing/Error/breaking scenarios for DUT. Own verification at module and/or full chip level. Proficiency in System Verilog and advanced UVM methodologies is a must. Good experience in System Verilog assertions.

Own the development of test plans, test environments and test suites used to verify complex Ethernet and Microcontroller SOC products. Prior experience as a verification lead is preferred. Prior experience of working with and guiding the junior members of the team is required.

Responsibilities

Product verification test plan specification Drive verification methodologies and practices Develop System Verilog verification IP Develop chip/block level test environments Develop and debug test suites Lead and mentor other verification engineers