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Infineon Technologies · Dallas, TX

Principal Engineer DSP PHY Digital Design

Dallas, TX, USFull-timeSenior individual contributorDesign

Listed on Infineon Technologies’s official careers site. Posted September 8, 2026. Check that it is still open and apply there.

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Job description

Build the future nobody's dreamed of yet... are you ready to rethink the impossible?

Architect and simulate DSP signal chains for automotive Ethernet PHYs: define features, performance targets, and algorithm specs for mixed-signal and digital teams RTL Design and Verification

  • Develop equalization and adaptation algorithms for wireline channels(e.g., FFE/DFE, adaptive filtering), including fixed-point considerations
  • Design and implement timing recovery/synchronization blocks (CDR, tracking loops), including jitter tolerance and stability/latency tradeoffs
  • Contribute to detection and coding / FEC integration: soft-information interfaces, performance/complexity tradeoffs, and linkKPIs
  • Build bit-true / fixed-point models and reference implementations primarily in C++ and MATLAB (Python optional, not core
  • Define verification metrics and stress tests (BER/FER, convergence time, corner cases) and partner with DV to ensure coverage
  • Support silicon bring-up and lab debug: correlate model ↔ silicon, root-cause issues, and iterate on algorithms/specs
  • Collaborate across architecture, design, verification, and applications to deliver implementable and testable solutions B.S. + 10 years (or M.S. + 7 years) in Electrical Engineering, Computer Engineering, or related field
  • Strong fundamentals in digital communications and DSP, including probability/statistics Practical experience in high-speed wireline DSP, including some mix of: FFE/DFE, adaptation, CDR, MLSD/Viterbi concepts, FEC integration, fixed-point modeling Strong C++ and MATLAB skills for algorithm development, modeling, and analysis Experience with automotive Ethernet PHY/SerDes constraints(robustness, low latency, interoperability, EMI resilience)
  • Familiarity with ADC-based receiver architectures and calibration concepts Experience translating algorithms into RTL-friendly specs(throughput/latency budgeting, memory/compute sizing, state-machine behavior)
  • Knowledge of link startup/training / autoneg concepts and system validation Exposure to standards work (e.g., IEEE 802.3) or cross-company technical leadership We are on a journey to create the best Infineon for everyone.

This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.

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