Engineer / Senior Engineer Design Verification

Job description

Develop test plans, tests, coverage model and debug fail tests.

Cross-functional collaboration

Partner closely with system architects, RTL design, FGPA, emulation, and firmware teams to translate design intent into constrained random tests. Bachelor's degree or above in Electronic, Electrical Engineering or Computer Science. Good knowledge of Universal Verification Methodology(UVM) and constrained random testing. Capability in SystemVerilog, Verilog, C/C++. Preferred to have experiences with Ethernet protocol such as ethernet switch, PHY, MAC.

Excellent critical thinking skills and capability to complete tasks before agreed deadlines. Excellent spoken and written communication skills in English. We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience.

Even if you don't meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon. Apply advanced verification techniques such as formal verification.