Lead Principal Engineer Design

Job description

Responsible for leading Physical Design and Timing Closure of lowpower SoCs targeted for IoT/MCU markets.

• Responsible to achieve die area, performance, power goals forhierarchical blocks and top. Drive physical design implementation which includes package co-design,floorplanning, power grid design and signoff, place and route, timingclosure, physical verification checks.
• Influence tools, flows and methodology activities to improve upon QoR. Interact with cross-functional team members to improve design,methodology and process aspects.

Technical Expertise

• Deep and broad understanding of physical design and timing convergence of hierarchical SoCs Expert user of industry standard tools and flow/automation forphysical design and signoff In-depth knowledge of process technologies and associated physicaldesign challenges Deep understanding of low power design techniques and implementation methodologies IFX Behaviours: Ability to solve complex problems by proactively involving expert networks
• Drives technical decisions in area of expertise and takesresponsibility for implementation
• Coordinates with colleagues and actively shares expertise with others
• Facilitates and encourages innovation within own domain of expertise Cooperates across boundaries and appreciates the contributions ofother people

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