Senior DfT Engineer

Job description

Job DescriptionAre you in search for a new challenge? Are you equipped with forward looking spirit and experienced in digital design flows and tools? Design-for-Test (DFT) is a multi-disciplinary field of growing complexity which involves cooperation among multiple VLSI engineering skills, including design, architecture, verification, backend, timing, test, ATE and reliability and more. Take the opportunity and join us as a

Senior DFT Engineer: Your roleDfT implementation inline with existing test methodology for advance process nodes Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST Closely work with physical design team to resolve timing constraints/issues Verify DFT circuitry and interface with other components/IPs and debug timing simulation issues

Debug and improve important DfT KPIs: test coverage/pattern efficiency Hierarchical retargeting Silicon bring-up, diagnosis and support for physical failure analysis Desired qualifications/skills: 6+ years of hands-on experience with DFT and test flows with commercial EDA tools for large and complex SOCsStrong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500

Std. and MBIST/LBISTExperience with one of the main EDAs providers: Synopsys DFT Complier, Tetramax, VCS, Tessent and Modus/Encounter tool suiteExperience in RTL simulation, synthesis, Linting, CDC and RDC checks, STA, DFT, quality metrics is a plusHands-on in Perl/Tcl/Python scriptingExcellent analytical, and problem-solving skills