Senior Physical Design Engineer

Job description

Your role Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below)In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route.Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing)

In charge with all validation/qualification tasks

Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixesBe part of the overall Low Power solution development and implementationDevelop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from toplevel to block level)Complete multiple design cycles of high complexity with little supervisionDesired qualifications/skills 8+ years in challenging RTL2GDSII work done on 10nm or below nodes with 500k –1million+ instances in designsPower user of

PnR and timing analysis CAD tools from Synopsys and/or CadenceGood knowledge of synthesis flow, insertDFT scan/coverage and optimizationExcellent floorplan, power plan, CTS, place, route, and timing closure skillsProficiency using Perl/TCL/Python scripting and MakefileExpertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skillExcellent EM/IR, DRC, LVS, ERC analysis and fixing skillsExperience with sign-off tape-out closure workAny top level – floor planning, pin assignment – tape out activities is a plusWe offer

Competitive Salary & BenefitsRespect for your private life and your choicesAll tools required for high performance in your fieldResponsible approach, long-term commitments, and stability