RTL Design Architect

Job description

Job DescriptionYour RoleLead architecture, integration, and verification strategy for high-speed connectivity IPs and chiplet interconnect solutions.Define PCIe/CXL/ UCIe subsystem architecture.Drive protocol compliance strategy.Review integration architecture and performance requirements.Lead interoperability and compliance planning.Guide verification and validation teams.Interface directly with customer architects.Support roadmap and future standard adoption.Your Profile12–20+ years in protocol/IP development.Deep expertise in PCIe

Gen4/5/6.UCIe architecture expertise.Chiplet ecosystem experience.Strong knowledge of protocol stack and LTSSM.Experience with root complex, endpoint, switch architectures.Experience integrating PCIe into large SoCs.Strong architecture and verification background.Knowledge of SerDes architecture.Good to HaveCXL protocol knowledge.HBM integration.Protocol compliance testing.System-level performance modeling.What You’ll Love About Working HereOpportunity to work on high-speed connectivity IPs.Collaborative work environment with focus on innovation and professional growth.Continuous learning opportunities to enhance technical and domain expertise.About

Capgemini in IndiaCapgemini is an AI‑powered global business and technology transformation partner, helping organizations realize their future through technology, data, and people.

With nearly 60 years of heritage, Capgemini is a responsible and diverse organization with 420,000 team members across more than 50 countries. The Group reported global revenues of €22.1 billion in 2024.Capgemini in India comprises nearly 235,000 team members working across 13 locations, including Bengaluru, Chennai, Hyderabad, Mumbai, Pune, Noida, Gurugram, and more. We deliver end‑to‑end services across strategy, technology, engineering, and operations.Make it real | www.capgemini.com/in‑en