OpenNash Jobs
Capgemini

Senior CAD Semiconductor Engineer

Athinai, Thessaloniki/Steliou KazantzidiSenior individual contributorOperations

Listed on Capgemini’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there.

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Job description

Technical SkillsEDA / CAD Flow ExpertiseStrong experience with full EDA flowsSimulation, synthesis, place & route, verification, DFT flowsTools from Cadence, Synopsys, Siemens EDA (Mentor Graphics)Tool validation, qualification, and deploymentStrong experience withEDA licensing systems (FlexLM/Flexera)Tool versioning, release management, and regression validationGood understanding ofRTL design, verification flows, and physical design constraintsInteraction between tools and silicon quality/productivityKnowledge in ISO26262, DO-254 is a plus

Infrastructure & AutomationStrong experience inLinux-based compute farms for EDA workloadsDistributed storage systems (NFS, parallel/distributed FS)CI/CD systems (Jenkins, GitLab CI or equivalent)Scripting and automationPython, Perl, Shell, TCLInfrastructure-as-code and automation mindsetExperience withMonitoring and performance optimizationBackup, disaster recovery, high availability AI / Modern Engineering ToolingPractical experience withAI/LLM-based tooling integration (e.g., Copilot, OpenAI, Gemini, Mistral)Hybrid AI infrastructure (cloud + on-prem GPU environments)Use cases such asWorkflow automationDebug assistanceKnowledge retrieval (RAG)Engineering productivity optimizationAdditional skillsObject-oriented programming conceptsFamiliarity withVersion control systems (Git, SVN, etc.)DevOps practices and toolchainsMissionDefine, deploy, and maintain EDA tool flows and CAD infrastructure supporting semiconductor design and verification activities across full

SoC lifecycle.Drive the evaluation, benchmarking, and integration of EDA tools (Cadence, Synopsys, Siemens EDA, Arteris) and associated flows to maximize productivity, reliability, and scalability.Own the engineering infrastructure environment (compute, storage, licensing, CI/CD, automation) required for advanced chip design workloads.Collaborate with design, verification, and physical implementation teams to ensure efficient, robust, and scalable tool usage.Explore and integrate AI/ML-based tooling and workflows to improve engineering productivity (automation, debugging, optimization, knowledge extraction).Ensure optimal trade-offs between performance, cost, scalability, and usability of the CAD environment.Act as a key technical interface between internal engineering teams, management, and EDA vendors.Provide regular reporting on tool performance, usage, and roadmap alignment.Main

ResponsibilitiesDefine, deploy, and maintain EDA flows for digital, mixed-signal, and verification activities (simulation, synthesis, P&R, DFT, signoff).Evaluate, benchmark, and qualify new EDA tools, releases, and methodologies before production deployment.Design and operate EDA infrastructure environments, includingCompute farms (Linux-based clusters for simulation and regression)Storage systems (NFS, distributed storage, backup/DR)License servers (FlexLM/Flexera)Develop and maintain automation frameworks forTool installation and configurationRegression and CI/CD pipelinesResource provisioning and monitoringImplement and manage CI/CD pipelines (e.g., Jenkins, GitLab CI) for design and verification workflows.Collaborate with engineering teams toOptimize tool usage and flowsDebug tool-related issuesImprove turnaround time and efficiencyMaintain strong interaction with EDA vendors (Cadence, Synopsys, Siemens)Tool support, issue resolution, roadmap alignmentLicensing strategy and capacity planningDefine and enforce best practices and standards for CAD usage and tool flows.Integrate AI-driven capabilities into engineering workflows, includingLLM-assisted scripting and automationAI-based log analysis, debug assistance, and workflow optimizationHybrid cloud/on-prem AI infrastructure for sensitive dataSupport security, compliance, and reliability requirements (e.g., ISO 27001 environments).

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