Experienced ASIC Analog Layout Engineer (m/f/d)

Job description

As an ASIC Layout Engineer (m/f/d), you will be responsible for the top-level integration of analog and mixed-signal ICs. You will drive the layout development process, ensuring robust, DRC-compliant designs with optimal area utilization. You will collaborate closely with analog circuit designers and other layout engineers to deliver high-quality silicon.

Key Responsibilities

Responsibility for top-level layout integration of analog/mixed-signal chips (analog on top) Defining toplevel floorplan, padframe design and bonding diagrams in coordination with other domains Coordinating with other layouters and drive floorplans according to the chip top level Generating and integrating analog layouts at block and chip level Performing pin placement, parasitic extraction, and layout optimization Responsibility for compliance with DRC, LVS, and support tape-out activities Collaborating with design engineers to meet speed, area, power, DFM, ESD, and EMC requirements

Qualifications

Academic degree in electrical engineering, microelectronics, physics or comparable qualification Longterm experience in analog layout design

• Proven experience in top-level layout integration
• Strong expertise in BCD technologies (65nm to 180nm) Deep understanding of deep submicron effects (parasitics, coupling, matching)
• Proficient in layout tools for design, DRC, LVS, and extraction
• Knowledge of analog circuit design Fluent English language skills (written and spoken), German language skills are a plus Applications from severely handicapped people are welcome.