ASIC Layout Engineer (m/f/d) - A OT AESS

Job description

As ASIC Layout Engineer (m/f/d) you generate the block and Chip layouts based on analog circuits / schematics in our Advanced Electronics & Semiconductor Solutions (AESS) department in Timisoara. The layout engineer chooses appropriate methods to reach robust DRC compliant layout with efficient area utilization. Layout engineer works very closely with the analog circuit designer. Tasks Creating and integrating analog layouts on block and top level Floor planning, pin placement, parasitic extraction Support design engineer to reach speed, area, power, DFM & ESD/EMV requirements DRC,LVS & Tape out support

Qualifications

• Master of Science / PhD in Electrical Engineering / Microelectronics / Physics or similar
• Bachelor degree in electronics engineering +2 years of layout design experience Good knowledge in area of analog circuit layout Nice to have experience in doing layouts in BCD technology (Technologies: 65 - 180nm) Good knowledge in the area of deep sub micron effects (parasitics, coupling, matching etc.) Basic understanding of layout tools (design, DRC, LVS, Extraction) Basic knowledge of analog circuit design

Languages Fluent English Capabilities

• Must be a team player with good communication and negotiation skills Customer focus (anticipates and understands the customers‘ needs) Motivation and inspiration (operates with integrity and demonstrates dynamism) Taking initiative