SoC Design Director

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Job Title

SoC Design Manager About the Role We are seeking an experienced and highly motivated SoC Design Manager to lead a team of engineers responsible for the design and development of next-generation System-on-Chip (SoC) solutions. The ideal candidate will possess strong technical expertise in digital design, excellent leadership skills, and a proven track record of delivering complex SoC projects from architecture through silicon.

Roles & Responsibilities Technology Background Experience of working on complex, large SoCs on latest technology nodes under tight schedules. Exposure to chiplets is desirable. Expertise around handling chip level design challenges around clocking, resets, power domains/distribution is a must Experience of working with DFT, PD, DV teams to solve critical technical challenges of cross-domain nature Experience of working on PCIE, UCIE, UALink, Ethernet products is highly desirable.

Must have working knowledge of embedded processors and firmware execution to enable key SoC level features SoC Design & Development Own the design and development of SoC subsystems from specification through RTL implementation. Review architecture and microarchitecture specifications and translate them into efficient design solutions. Oversee RTL coding, integration, and design reviews to ensure quality and compliance with design standards.

Drive design closure while meeting performance, power, area, and schedule targets. Project Execution Define project plans, resource allocation, and execution timelines. Track deliverables and ensure milestones are met on schedule. Identify technical and program risks and implement mitigation plans. Provide regular status updates to leadership and key stakeholders. Cross-Functional Collaboration Work closely with Architecture, Verification, DFT, Physical Design, Firmware, and Software teams throughout the development cycle.

Support verification planning and debug activities to ensure robust design quality. Collaborate with implementation teams to address synthesis, timing, power, and integration challenges. Quality & Process Improvement Establish and enforce design methodologies, coding guidelines, and best practices. Drive continuous improvement in design processes, productivity, and quality metrics. Ensure designs meet functional, performance, and reliability requirements.

Silicon Bring-Up & Product Support Support post-silicon validation, debug, and product qualification activities. Assist in root-cause analysis and resolution of silicon issues when required. Provide technical leadership for future product enhancements and next-generation designs. Team Leadership & Management Lead, mentor, and manage a team of SoC/RTL design engineers. Drive team performance, career development, and succession planning.

Participate in hiring and onboarding of new team members. Foster a collaborative and high-performance engineering culture.

Required Qualifications

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field. 15+ years of experience in ASIC/SoC design and development. 5+ years of experience leading engineering teams or technical projects. Strong expertise in RTL design using Verilog/SystemVerilog. Experience with SoC integration, interconnects, memory subsystems, and industry-standard protocols such as AXI, AHB, APB, PCIe, USB UALink , Ethernet, or DDR.

Strong understanding of the complete ASIC development lifecycle. Experience working with Verification, Physical Design, DFT, and Post-Silicon Validation teams. Excellent debugging, problem-solving, and communication skills. Experience with AI/ML, networking, datacenter, automotive, or high-performance computing SoCs. Knowledge of low-power design techniques and clock/reset architectures. Experience with scripting languages such as Python, Perl, or Tcl.

Prior experience delivering multiple successful tape-outs. Experience managing globally distributed engineering teams. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.