Senior Digital Design

Job description

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers.

With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X . DIGITAL DESIGN ENGINEER The Group The Joint Development Team (JDT) is a small, independent, cross-disciplinary group whose charter is to accelerate the development of key components, systems, algorithms, and techniques necessary to advance the state of the art in targeted areas and to collaborate with focused product development teams to get these advances to the marketplace.

Current and future research areas include advanced medical devices, energy metering and fault detection, high-speed imaging, security electronics, ultra-precision references and data converters. The group is led by Analog Devices Fellow JED Hurwitz, a pioneer in CMOS imaging, recognized expert in ultra-high precision, and of broad industrial experience. The group culture aims to foster a challenging, exciting, and supportive environment.

The team members must be comfortable working on a wide variety of products and technologies in a fast-paced and agile environment and will be exposed to various groups across the corporation’s many sites through all stages of the development cycle. The Role The P3 Digital Design Engineer contributes to RTL design, subsystem implementation, and mixed - signal integration of digital logic blocks under the mentorship of senior designers.

Work spans RTL creation, verification collaboration, and supporting implementation flows. The engineer is expected to develop skills related to digital verification . The engineer may switch between design and DV roles depending on project needs once sufficiently trained.

Key Responsibilities

Write RTL for digital blocks based on specifications. Perform lint, CDC analysis, and support DFT integration. Assist in writing functional testcases and simple UVM components. Collaborate with DV engineers for coverage closure and bug resolution. Support AMS co ‑ simulation and integration with analog blocks. Work with physical design teams on synthesis and timing. Train and develop skills in digital design verification

Minimum Qualifications

BS or MS in ECE, EE, CpE , or equivalent. 2–5 years digital design experience, or strong NCG background. Proficiency in SystemVerilog /Verilog; familiarity with UVM preferred. Experience with scripting languages (Python/Perl/TCL). Basic understanding of AMS modeling and mixed ‑ signal flows is a plus. Strong analytical, problemsolving , and communication skills. Capable of performing indepen den t research and self study For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.

Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type

Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days