ASIC Design Engineer, Satellite Communication

Job description

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.

Come work at Amazon!

We're hiring a ASIC Digital Design Engineer within a high performance ASIC design team. This team is using industry leading methodologies to develop proprietary IP’s.

The Role

Be part of Leo’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a state-of-the-art wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.

In this role you will:

· Implement wireless system architecture in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level validation.

• Build complex, high-performance digital solutions and develop solutions by leveraging AI-assisted techniques optimizing customer experience (throughput, latency and availability) while meeting power and cost constraints.
• Drive high quality designs for first-time right silicon solutions, and meeting the PPA objectives
• Work with the verification team and participate in System level verification using test benches constructed using UVM/System C/DPI-C including test plan development

Export Control Requirement

Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Key job responsibilities

· Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets.

• Define, configure and integrate key IP blocks for SoC
• Control plane architecture and implementation for PHY subsystem for the SoC
• Configure, instantiate and integrate 3rd party IP blocks
• Understand low power design & the impact of DFT on the blocks
• Perform initial synthesis & timing analysis
• Assist verification team in unit verification including test plan development
• Assist with debug and bring-up