Principal Silicon Product Engineer
Listed on Alphabet’s official careers site. Listed as of October 13, 2026. Check that it is still open and apply there.
Apply on Alphabet’s careers site →Job description
Minimum qualifications
15 years of relevant experience in Semiconductor Product Engineering, Silicon Architecture, Foundry Engineering, or Technical Sourcing Engineering.
Experience with semiconductor product lifecycle
design tape-out, wafer fab processing, parametric yield analysis, advanced packaging/assembly, and high-volume test engineering (ATE/SLT). Experience evaluating and scaling leading-edge nodes (3nm, 2nm, and beyond) and heterogeneous packaging technologies (2.5D/3D, CoWoS, chiplets, HBM). Experience covering both Custom ASIC/COT flows and standardized high-performance compute silicon (GPUs, x86/ARM CPUs, high-speed networking, and memory architectures).
Preferred qualifications
Master’s degree or Ph.D. in Electrical Engineering, Microelectronics, Materials Science, or related technical field. Experience with silicon execution vehicles (eTV/mTV), silicon photonics integration, advanced cooling/thermal interfaces, and custom AI accelerator hardware bottlenecks. About the job As the Principal Silicon Product Engineer, you will serve as the chief technical authority for the Silicon Sourcing organization bridging hardware engineering design, global manufacturing ecosystems, and strategic sourcing across the entire silicon lifecycle.
While our commercial leads focus on master service agreements, capacity reservations, and multi-billion-dollar contract structures, you will lead the technical arm of the organization. You will drive deep architectural, manufacturing, and product engineering evaluations across both Custom Silicon (ASICs/COT: TPUs, gSOC, custom networking/accelerators) and Off-the-Shelf (OTS: GPUs, x86 CPUs, Memory, Storage, Strategic Silicon).
You will be deeply embedded across all phases of the silicon product lifecycle—from early silicon architecture and process node selection to NPI, DFM/DFT validation, wafer fab yield modeling, advanced packaging integration, and test engineering optimization. You will be the authoritative technical partner to internal Platforms Engineering, Systems Architecture, and Cloud Supply Chain Operations teams, translating complex semiconductor physics and manufacturing realities into actionable sourcing leverage, risk mitigation, and performance breakthroughs.
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