Principal Memory Sub-System Validation Lead

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.

Join us and, together, we’ll advance your career.

THE ROLE

The Data Center Graphics and Accelerated Computing Validation Team is looking for a dynamic and energetic lead to join our growing post-silicon validation team. The Memory sub-system validation lead is responsible to drive and deliver pre- and post-silicon validation and characterization of on-die High-Bandwidth Memory (HBM) on AMD’s Datacenter GPU (Machine Instinct product). High Bandwidth Memory sub-system is at heart of complex technology that delivers industry leading Datacenter solutions for Machine Learning (ML), and High-Performance Computing (HPC).

In this wide-ranging role, validation lead is the critical interface between DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams to ensure that advanced memory technologies are delivered from architecture to mass production to AMD’s quality and industry standards. The validation team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON

An experienced self-starter with the ability to execute complex test plans independently and collaborate with cross-function teams to debug and resolve issues. As a valued team member, you are expected to lead by example, and mentor junior engineers. You should be hands-on with lab tools and comfortable working in a lab environment.

KEY RESPONSIBILITIES

The Memory Sub-system Validation Lead’s responsibility includes all aspects of pre- and post-silicon validation from planning, execution and debug. Develop and execute test plans for HBM Functional and Electrical Validation (PVT Shmoo Characterization). The sought-after candidate possesses extensive knowledge of high bandwidth memory subsystem, including SoC memory architecture, Unified Memory controller, PHY design and high speed IO interface, DRAM device, and associated calibration/training mechanisms.

We are looking for

Extraordinary leadership skills and ability to inspire team members with an innate ability to see the bigger picture. Excellent debugging skills. Proven ability to drive resolution of critical problems, while under pressure. Ability to understand complex technical discussions, extract action plans, and to succinctly summarize complex details for executive reporting Ability to apply knowledge of other high-speed, high-performance memory technologies Experience working with major DRAM memory vendors and validation of DRAM device is a plus.

Debug skills to root cause post-production issues, customer returns Able to comfortable working in lab environment PREFERRED EXPERIENCE: Significant experience in DDR , LPDDR , HBM SoC validation, verification and debug of High-Bandwidth Memory sub-system

• Develop functional, electrical validation plans for memory features, align cross-functional teams on the support and validation plans
• Drive debug in post silicon, root-cause problems and steer the team to the best corrective action to move forward
• Collaborate and drive memory related silicon issues across multi-functional teams: Design, Verification, Silicon Validation, Productization, System Hardware and Software Hands-on experience in using industry standard JTAG, I2C, Tester and Lab tools
• Strong programming skills (C/C++, Python) and comfortable working on Linux or Windows platforms Experience in developing test cases for Machine Learning, High Performance Computing Able to work as a team and work efficiently in a dynamic environment and on multiple projects ACADEMIC CREDENTIALS: Bachelors or Masters in Electrical or Computer Engineering LOCATION: Santa Clara, CA This role is not eligible for visa sponsorship. #LI-SL2 Benefits offered are described: AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.