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Advanced Micro Devices (AMD) · Santa Clara, California

Design Verification Engineer

Santa Clara, CaliforniaFull-timeDesign

Listed on Advanced Micro Devices (AMD)’s official careers site. Posted July 29, 2026. Check that it is still open and apply there.

Apply on Advanced Micro Devices (AMD)’s careers site →

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

THE ROLE

We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

THE PERSON

You have a passion for modern, complex processor architecture, asic/soc verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. A successful candidate will work with senior silicon design and firmware engineers.

The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES

Develop/Maintain tests for functional verification. Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues. Work on functional & code coverage verification.

Provide technical support to other teams PREFERRED EXPERIENCE

Experience with Verilog, System Verilog and modern verification libraries like UVM Experience with C/C++ Strong ASIC design verification experience Experience / Background with DDR or Memory Controller. PHY Verification is a plus Experience with scripting languages like Python, Perl and TCL is a plus. Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Proficient in debugging RTL code using simulation tools ACADEMIC CREDENTIALS: Bachelors or Master’s or Ph.D. degree in computer engineering/Electrical Engineering LOCATION : Santa Clara, CA ( open to other AMD locations) This role is not eligible for visa sponsorship. #LI-SL3 Benefits offered are described: AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

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