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Zhongji Innolight · 上海

# UCIe PHY互连数字架构工程师

上海 

Listed on Zhongji Innolight’s official careers site. Posted July 22, 2026. Check that it is still open and apply there.
[Apply on Zhongji Innolight’s careers site →](https://zj-innolight.jobs.feishu.cn/index/position/7665163305363261732/detail)

[OpenNash Jobs](https://jobs.opennash.com/) / [Zhongji Innolight](https://jobs.opennash.com/companies/zhongji-innolight/) / UCIe PHY互连数字架构工程师

## Job description

1. 职位目标 下一代 Chiplet（芯粒）高速UCIe 协议互连技术方案数字实现。 2. 核心职责

### 技术研发
- 设计与开发符合 UCIe 1.1/2.0 规范 的物理层（PHY）方案。

### 建模与仿真
- 负责高速链路（Link Layer）的信号完整性（SI）和电源完整性（PI）仿真。

### 协议实现
- 优化 UCIe Streaming 协议在传输环境下的映射，确保数据在链路上的低延迟与高可靠性。

### 流片支持
- 参与 SoC 的前端设计、验证及后期实验室回片调试（Bring-up）。

### 教育背景
- 微电子、电子工程、通信工程或计算机科学等相关专业。
- 技术要求 (Must-have)

### 协议基础
- 深入理解 UCIe、PCIe Gen6/7 或 CXL 协议规范。

### 硬件经验
- 具备高速 SerDes 或高速接口（PHY）的设计与验证经验。

### 工具链
- 熟练使用 Cadence Virtuoso, ADS, Hspice 或 Verilog/SystemVerilog 进行模拟或数模混合设计。
- 加分项 (Nice-to-have)
- 具备 AI 加速器（GPU/NPU）芯片间互连（Scale-out/Scale-in）架构设计经验。

## At a glance
- Posted by the employer: Jul 22, 2026
- First seen by OpenNash: Oct 20, 2026
- Last checked: Oct 20, 2026
- Listed for: 90 days
- Location: 上海[Apply on Zhongji Innolight’s careers site →](https://zj-innolight.jobs.feishu.cn/index/position/7665163305363261732/detail)

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