[Skip to main content](#main-content)

[OpenNash Jobs](https://jobs.opennash.com/)
[Hiring report](/reports/hiring/) · [All Western Digital jobs](https://jobs.opennash.com/companies/western-digital/) · [Search jobs](/search/)

Western Digital · San Jose, CA

# Principal RFIC Design Engineer

San Jose, CA, United States Full-time Senior individual contributor Design 

Listed on Western Digital’s official careers site. Posted October 14, 2026. Check that it is still open and apply there.
[Apply on Western Digital’s careers site →](https://jobs.smartrecruiters.com/WesternDigital/744000155570360-principal-rfic-design-engineer)

[OpenNash Jobs](https://jobs.opennash.com/) / [Western Digital](https://jobs.opennash.com/companies/western-digital/) / Principal RFIC Design Engineer

## Job description

### ESSENTIAL DUTIES

AND RESPONSIBILITIES: Designer will be responsible for the design of high performance analog and mixed-signal circuit blocks. Responsibilities include transistor level, block level and module level circuit architecture, design, simulation, optimization, layout supervision, layout verification, preparation of test plan for the test group, product characterization, reliability and yield assessment and modeling, simulation to bench and bench to test correlation, bench evaluation both at silicon level and at applications level, and documentation.

Job responsibilities require ability to communicate at all levels and with cross functional groups. Candidate must have good verbal and written communications skills and demonstrated track record of circuit innovation, must be a team player, be adaptable, and accept constructive criticism

## Qualifications

Must have hands-on design and development experience in analog and mixed-signal integrated circuit Must have experience in at least one preferably multiple area of full CMOS circuit design and development in: Amplifiers – operational, instrumentation, wide-bandwidth etc. PMIC – Linear and switched regulators, Low-drop out regulators etc.

Data converters – ADC, DAC, Flash and SAR type
- Must have experience in 40nm and below CMOS technology
- Must have a demonstrable track record of successful design releases and mass production
- Must have thorough knowledge of industry standard EDA tools (Cadence, Mentor, Siemens, Ansys etc.) Experience with analog layout techniques of mismatch reduction, gradient suppression, parasitic effects minimization Experience with floor planning, block level routing and top level chip routing
- Knowledge of high performance and deep CMOS analog reliability considerations such as EM-IR, SOA and VDR and relevant mitigation techniques Functional knowledge of logic digital circuits and understanding of basic digital design flow Experience working with distributed design teams a plus
- Must possess strong written and verbal communication skills BSEE with minimum
- 10+ years of experience MSEE with minimum
- 8+ years of experience PhD with minimum
- 4+ years of experience

## At a glance
- Posted by the employer: Oct 14, 2026
- First seen by OpenNash: Jul 11, 2026
- Last checked: Oct 18, 2026
- Listed for: 99 days
- Location: San Jose, CA, United States
- Employment type: Full-time[Apply on Western Digital’s careers site →](https://jobs.smartrecruiters.com/WesternDigital/744000155570360-principal-rfic-design-engineer)

## More jobs at Western Digital

### [Organization Effectiveness & Design Lead](https://jobs.opennash.com/companies/western-digital/jobs/3f82f2862087d4ad0ae5/)

San Jose, CA, United States

### [Quantum Device Design Engineering Scientist](https://jobs.opennash.com/companies/western-digital/jobs/c03482362d68e88f5f08/)

San Jose, CA, United States

### [Real Estate Design and Construction Manager](https://jobs.opennash.com/companies/western-digital/jobs/f4dd3a490f17351152b6/)

San Jose, CA, United States

### [Associate, Corporate Development Analyst](https://jobs.opennash.com/companies/western-digital/jobs/4889658d1c7d80120d4c/)

San Jose, CA, United States

### [Associate, Corporate Strategy Analyst](https://jobs.opennash.com/companies/western-digital/jobs/79d839611fcd2fe56fe6/)

San Jose, CA, United States

## Similar jobs at other companies

### [Principal Engineer- Design](https://jobs.opennash.com/companies/on-semiconductor/jobs/26dd71f1686177c9fedc/)

ON Semiconductor · San Jose, CA, United States

### [Principal Design Verification Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/d3fd6c1b5d0f2416d46e/)

Renesas Electronics · San Jose, CA, United States

### [RFIC Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/25a9f51d48491129e56c/)

Qualcomm · San Diego, California, United States of America

### [Senior RFIC Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/7f370848f9d5f37b6f25/)

Qualcomm · Santa Clara, California, United States of America

### [Circuit Design Engineer, Principal](https://jobs.opennash.com/companies/lockheed-martin/jobs/78cd34d8da60b7b89600/)

Lockheed Martin · Goleta, CA

OpenNash lists jobs from employers’ own careers sites and does not handle applications.
Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)