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Western Digital · San Jose, CA

# Chief Memory Chip Design Engineer & Architect

San Jose, CA, United States Full-time Executive Design 

Listed on Western Digital’s official careers site. Posted October 30, 2026. Check that it is still open and apply there.
[Apply on Western Digital’s careers site →](https://jobs.smartrecruiters.com/WesternDigital/744000158814244-chief-memory-chip-design-engineer-architect)

[OpenNash Jobs](https://jobs.opennash.com/) / [Western Digital](https://jobs.opennash.com/companies/western-digital/) / Chief Memory Chip Design Engineer & Architect

## Job description

This role is the most senior technical individual contributor in memory design. Owns end-to-end product architecture from concept through silicon qualification, arbitrates the power/performance/area trade-offs that set competitiveness, and is the final technical authority across design, process and product engineering.
- Define the memory subsystem architecture (array, periphery, I/O, redundancy, test, reliability) and turn product requirements into a design spec
- Drive floorplan and physical architecture: array efficiency, periphery partitioning, power delivery, die-level signal integrity
- Own the multi-generation roadmap: node migration, density and performance scaling Decide cross-functional trade-offs across process integration, circuits, DFT, packaging and controller/firmware interfaces
- Own design methodology and EDA/CAD strategy: tools, flows, vendors, licenses
- Mentor senior and principal engineers through architecture and design reviews
- Represent the architecture to executives, customers, foundry partners and standards bodies

## Qualifications

Required MS/PhD in EE, CE or related field 15+ years in memory or mixed-signal IC development; 5+ as architect or chief engineer 2+ memory products owned from architecture through production silicon Deep advanced CMOS FinFET expertise: layout, variability, reliability, DFM Memory architecture breadth (DRAM, NAND/NOR, SRAM, emerging NVM), depth in one Modern Cadence/Synopsys custom and digital flows through full-chip sign-off Owned EDA/CAD strategy; led multi-site programs through influence Preferred Embedded memory IP integration into SoCs; memory-controller co-design Foundry engagement on PDKs, test chips and DTCO Emerging NVM architecture; JEDEC, patents or publications

## At a glance
- Posted by the employer: Oct 30, 2026
- First seen by OpenNash: Oct 25, 2026
- Last checked: Nov 1, 2026
- Listed for: 7 days
- Location: San Jose, CA, United States
- Employment type: Full-time[Apply on Western Digital’s careers site →](https://jobs.smartrecruiters.com/WesternDigital/744000158814244-chief-memory-chip-design-engineer-architect)

## Hiring at Western Digital
- Open jobs: 345
- New in the last 7 days: After two weekly collections
- Tracked since: Jul 11, 2026

[All Western Digital jobs](https://jobs.opennash.com/companies/western-digital/) · [Weekly hiring report](/reports/hiring/)

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