[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) Texas Instruments · Dallas, TX # Layout Design Intern-Dallas,TX Dallas, TX, United States Full-time Early career Design Listed on Texas Instruments’s official careers site. Posted November 2, 2026. Check that it is still open and apply there. [Apply on Texas Instruments’s careers site →](https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25019249) [OpenNash Jobs](https://jobs.opennash.com/) / [Texas Instruments](https://jobs.opennash.com/companies/texas-instruments/) / Layout Design Intern-Dallas,TX ## Job description Change the world. Love your job. Texas Instruments is currently seeking a Layout Design Intern to join the team. In this role, you will have the opportunity to work in a team that creates semiconductors that go into exciting and cutting-edge technologies like smart phones, cars, satellites, robotics, and numerous other applications. You will develop and prepare multi-dimensional layouts and detailed drawings of semiconductor devices from schematics and related geometry provided by design engineering. About the job This position will require the creation and management of integrated circuit (IC) layouts from start to finish. Using CAD software, you will floorplan, design, implement and verify analog integrated circuits. You will support the design engineers to reach goals in precision, speed, area, reliability, power and ESD requirements. You will also work with PE/Packaging engineers to assure reliable production capability and proper data preparation for fab hand-off, documentation, and archive. Some of your responsibilities will include, but will not be limited to: Collaborating with Analog and Digital design teams and the global layout design community Understanding manufacturing rules and implementing layout to be robust and area-efficient Writing layout specifications, checking dimensions, and verifying completed art work Verifying that the layout is compliant with Design Rule Checks (DRCs) and Electrical Rule Checks (ERCs) Participating in layout design reviews Creating design flow automation Texas Instruments will not sponsor job applicants for visas or work authorization for this position. ## Qualifications - Minimum requirements Currently pursuing an Associates or Bachelors degree in Electrical Engineering, Engineering Technology, or related degree Minimum 3.0 out of 4.0 GPA Preferred qualifications: Working knowledge of electrical circuits such as resistance, capacitance, voltage and current - Familiarity with Unix/Linux, Cadence Virtuoso, Assura LVS, DRC, or similar mixed signal EDA tools (Mentor, Synopsys) Basic proficiency in one or more coding languages such as Perl, Python, C, Cadence SKILL Familiarity with semiconductor device physics, analog circuits and their layout sensitivities Working knowledge of semiconductor processes and IC production flow including BJTs, Diodes, FETs, passive components, packaging and thermal design Working knowledge of layout-related matching techniques, on-chip parasitic sources and minimization, routing impedances and electromigration, and crosstalk - Ability to establish strong relationships with key stakeholders critical to success, both internally and externally - Strong verbal and written communication skills - Ability to quickly ramp on new systems and processes - Demonstrated strong interpersonal, analytical and problem-solving skills - Ability to work in teams and collaborate effectively with people in different functions - Ability to take the initiative and drive for results - Strong time management skills that enable on-time project delivery Put your talent to work with us as a Layout Design Intern– change the world, love your job! ## At a glance - Posted by the employer: Nov 2, 2026 - First seen by OpenNash: Nov 8, 2026 - Last checked: Nov 8, 2026 - Listed for: 6 days - Location: Dallas, TX, United States - Employment type: Full-time[Apply on Texas Instruments’s careers site →](https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25019249) ## Hiring at Texas Instruments - Open jobs: 905 - New in the last 7 days: After two weekly collections - Tracked since: Jul 10, 2026 [All Texas Instruments jobs](https://jobs.opennash.com/companies/texas-instruments/) · [Weekly hiring report](/reports/hiring/) ## More jobs at Texas Instruments ### [Layout Design Manager](https://jobs.opennash.com/companies/texas-instruments/jobs/d2f699ca6b8ba59a6f5e/) Dallas, TX, United States ### [Layout Designer](https://jobs.opennash.com/companies/texas-instruments/jobs/d385e09c361c1be8f64b/) Dallas, TX, United States ### [Optical Design Engineer](https://jobs.opennash.com/companies/texas-instruments/jobs/0821340062ac6703b858/) Dallas, TX, United States ### [Silicon Photonics Design Engineer](https://jobs.opennash.com/companies/texas-instruments/jobs/9da234139ff3d0dab2e5/) Dallas, TX, United States ## Similar jobs at other companies ### [Mask Layout Designer](https://jobs.opennash.com/companies/qualcomm/jobs/382a8c6e51bc76d22364/) Qualcomm · Tijuana, Baja California, Mexico ### [PCB Layout Design Engineer](https://jobs.opennash.com/companies/lockheed-martin/jobs/223f969626c59a23169e/) Lockheed Martin · Orlando, FL ### [Memory Mask Layout Designer](https://jobs.opennash.com/companies/qualcomm/jobs/08212c6623250088c429/) Qualcomm · Tijuana, Baja California, Mexico ### [Microwave Design and Layout Engineer](https://jobs.opennash.com/companies/microsoft/jobs/81da72c4c6471bd01395/) Microsoft · United States, Washington, Redmond ### [Layout Technician - 2nd Shift](https://jobs.opennash.com/companies/eaton/jobs/a41c26270f9c59653672/) Eaton · Troy, Illinois, USA OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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