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Taiwan Semiconductor · Yokohama or Osaka, JP

# Layout Engineer

Yokohama or Osaka, JP Operations 

Listed on Taiwan Semiconductor’s official careers site. Listed as of October 19, 2026. Check that it is still open and apply there.
[Apply on Taiwan Semiconductor’s careers site →](https://ro.careers.tsmc.com/job/Yokohama-or-Osaka-Layout-Engineer-14/776190210/)

[OpenNash Jobs](https://jobs.opennash.com/) / [Taiwan Semiconductor](https://jobs.opennash.com/companies/taiwan-semiconductor/) / Layout Engineer

## Job description

### Job Description

RDR design rules optimization.
- Develop Standard Cell/IO Library Memory and Analog IPs in advanced technology.
- Develop Memory IPs, Compiler and Test Vehicle.
- Develop Standard Cell/IO Library and Analog.

### IPs
- Provide design rules trade-off on area and performance.
- Find layout solution for Standard Cell/IO Library Memory and Analog IPs to reduce RDR impact on area.

### Qualifications

- BCH and above degree in EE or Engineering related field with 3+ years of working experiences.
- Expertise on std. Cell, SRAM, IO and analog layout and familiar with customers usage on those IPs.
- Layout expertise of SRAM (first priority), Standard cell, IO, Analog, Process with Virtuoso and Device background will be a plus.
- Highly welcome candidates who have less custom layout experience but have good related design experience, working attitude and are self-motivated.
- Good command of Japanese.
- Be able to communicate with customer in English is a plus. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 19, 2026
- Last checked: Oct 19, 2026
- Listed for: Under a day
- Location: Yokohama or Osaka, JP[Apply on Taiwan Semiconductor’s careers site →](https://ro.careers.tsmc.com/job/Yokohama-or-Osaka-Layout-Engineer-14/776190210/)

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