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Taiwan Semiconductor · Kumamoto, JP

# JASM - Quality & Reliability - Failure Analysis Engineer (5524)

Kumamoto, JP Manufacturing & Production 

Listed on Taiwan Semiconductor’s official careers site. Listed as of October 19, 2026. Check that it is still open and apply there.
[Apply on Taiwan Semiconductor’s careers site →](https://ro.careers.tsmc.com/job/Kumamoto-JASM-Quality-&-Reliability-Failure-Analysis-Engineer-%285524%29-43-8691102/1050894066/)

[OpenNash Jobs](https://jobs.opennash.com/) / [Taiwan Semiconductor](https://jobs.opennash.com/companies/taiwan-semiconductor/) / JASM - Quality & Reliability - Failure Analysis Engineer (5524)

## Job description

The responsibilities of this position will involve efforts in: Operation of instruments, development of new sample preparation methodology, TEM/SEM based analytical analysis and analytical instrument and analytical software development. Data interpretation and reporting and Interaction with requestor from both R&D and Fab operation for technology development and failure analysis. Responsible for identifying, developing, and implementing advanced TEM (Transmission Electron microscopy) metrology, SEM, FIB, BSE, EDX, EBSD and etc, and analytical analysis techniques at nano/atomic scale to support company research and production.

Looking for experienced TEM/SEM experts specialized in following fields: Responsibilities (Immediately after hiring)
- Computational microscopy and with hands-on capabilities.
- Experts in electron diffraction theory, simulation, and applications.
- In-depth understanding of electron optics and image simulations.
- TEM/SEM based analytical analysis (e.g., EELS, EDS, BSE, EDX, EBSD, and CL), analytical instrument, and analytical software development. (Scope of change)There is a reassignment to the work specified by the company.

### Minimum Qualifications
- Master or above in Material Science, Physics, Chemistry or related science and engineering disciplines
- English- Business level is required.
- Knowledge of semiconductor process and SPC is a plus.
- Strong communication and interpersonal skills are essential such as communicate with TEM analysis requestors from process or integration engineers.
- Semiconductor process experience is a plus.
- Good demonstration on team leadership

### Preferred Qualifications

1. Mandarin communication level is a plus to well communicate with assignee and HQ engineers. Working Conditions
- Location - （Immediately after hiring) 4106-1 Haramizu, Kikuyou-machi, Kikuchi-gun, Kumamoto, 869-1102 (Scope of Change) Location determined by the Company
- Working Days & Hours
- Mon.-Fri. 8:30-17:30, holiday-duty once per month
- Benefits, Welfare
- Health insurance, Employee pension, Employment insurance, Industrial accident compensation insurance, Pension plan, Retirement allowance plan, Annual leave,

### Commuting allowance
- Actual expenses (maximum 50,000 yen/month), Housing allowance (In accordance with company's regulations)
- Business Holiday

### Saturdays, Sundays & Holidays, Vacation regulations
- GW vacation, Summer vacation, Year-end and New Year vacations ※Follows the vacation regulations according to the company calendar
- Recruitment Process - 2-3 interviews+ Aptitude Test→ offer

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 19, 2026
- Last checked: Oct 19, 2026
- Listed for: Under a day
- Location: Kumamoto, JP[Apply on Taiwan Semiconductor’s careers site →](https://ro.careers.tsmc.com/job/Kumamoto-JASM-Quality-&-Reliability-Failure-Analysis-Engineer-%285524%29-43-8691102/1050894066/)

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