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Synopsys · Hsinchu, Taiwan

# ASIC Design Verification Engineer, Staff - Principal

Hsinchu, Taiwan Senior individual contributor Design 

Listed on Synopsys’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there.
[Apply on Synopsys’s careers site →](https://careers.synopsys.com/job/hsinchu/asic-design-verification-engineer-staff-principal/44408/100703928160)

[OpenNash Jobs](https://jobs.opennash.com/) / [Synopsys](https://jobs.opennash.com/companies/synopsys/) / ASIC Design Verification Engineer, Staff - Principal

## Job description

### About Synopsys

At Synopsys, we drive the innovations that shape how we live and work—self-driving cars, artificial intelligence, cloud computing, 5G, and the Internet of Things. As a leader in advanced chip design and software security technologies, we empower the Era of Smart Everything. If you share our passion for innovation, we invite you to join our team.

### About Silicon IP

Our Silicon IP business enables customers to integrate advanced capabilities into SoCs quickly and efficiently. We offer the industry’s broadest portfolio of silicon IP, including logic, memory, interfaces, analog, security, and embedded processors. Our solutions help customers meet unique application requirements and accelerate differentiated product delivery with reduced risk.

### Job Responsibilities
- Develop verification strategies and plans for ASIC/SoC projects
- Define and implement testbench architecture and methodologies
- Build testbench infrastructure and verification components
- Create verification item lists, coverage models, and checkers
- Provide clear, metric-driven reports on verification progress Break down tasks, develop schedules, and manage deliverables
- Lead and coordinate design review meetings
- Serve as a technical expert and mentor within the team Key Qualifications: Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) with 15+ years of relevant experience Extensive hands-on experience creating test environments from functional specifications using UVM/VMM/OVM Proven expertise in constraint random verification, coverage closure, and failure analysis
- Proficiency in SystemVerilog, UVM, and object-oriented verification methodologies Experience with Verilog/SystemVerilog coding and simulation tools
- Solid understanding of SoC/ASIC design flows and backend processes
- Knowledge of one or more interface protocols: DDR, PCIe, AMBA (AMBA2, AXI, CHI), SD, eMMC, Ethernet, USB, MIPI Experience working in Unix environments Strong English communication skills, both written and verbal
- Ability to work independently, drive innovation, and solve complex problems
- Strong team player with excellent interpersonal skills Preferred Qualifications: Experience with formal verification techniques
- Knowledge of C/C++, Perl, Python, and TCL scripting Understanding of firmware or embedded software development Experience with functional safety standards (ISO26262, FMEDA)

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 11, 2026
- Last checked: Oct 18, 2026
- Listed for: 7 days
- Location: Hsinchu, Taiwan[Apply on Synopsys’s careers site →](https://careers.synopsys.com/job/hsinchu/asic-design-verification-engineer-staff-principal/44408/100703928160)

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