[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Synopsys jobs](https://jobs.opennash.com/companies/synopsys/) · [Search jobs](/search/) Synopsys · Hanoi, Viet Nam # Analog Layout Design, Staff Engineer in Da Nang / Ha Noi Hanoi, Viet Nam Senior individual contributor {'@type': 'MonetaryAmount', 'currency': '', 'value': {'@type': 'QuantitativeValue', 'unitText': ''}} Design Listed on Synopsys’s official careers site. Posted October 15, 2026. Check that it is still open and apply there. [Apply on Synopsys’s careers site →](https://careers.synopsys.com/job/hanoi/analog-layout-design-staff-engineer-in-da-nang-ha-noi/44408/101981588832) [OpenNash Jobs](https://jobs.opennash.com/) / [Synopsys](https://jobs.opennash.com/companies/synopsys/) / Analog Layout Design, Staff Engineer in Da Nang / Ha Noi ## Job description ### Alternate Job Titles Analog Layout Staff Engineer Analog IC Layout Staff Engineer Custom Layout Staff Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. ### You Are You are an experienced Analog Layout Senior Engineer with a strong background in custom layout design. You are passionate about technology and thrive in a collaborative environment. With at least 5 years of experience in custom layout, you are proficient with layout entry tools such as Cadence and Synopsys and layout verification tools like Mentor Calibre and Synopsys ICV. You possess a solid understanding of semiconductor fabrication processes and MOSFET fundamentals. Your expertise in high-speed layout techniques, ESD, Latchup, Antenna, and EMIR is a testament to your deep technical knowledge. Additionally, you have experience mentoring junior engineers and leading layout teams to achieve project goals. Your excellent English communication skills, team-oriented mindset, and self-motivation make you an ideal fit for our dynamic team. You are humble, honest, and always eager to learn and grow in your career. ### What You’ll Be Doing Working on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees. Floor planning, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics. Applying Analog Layout techniques to ensure design meets performance with minimum area and good yield. Building and enhancing layout flow for faster, higher quality design processes. Performing layout verification for DRC/LVS/ERC/ANT/ESD/DFM. Conducting PERC verification for ESD/LUP checks. Completing all design quality checks and data quality checks. Collaborating with Place and Route engineers to integrate analog layouts into the top level. Working with the Package team to ensure the integration of top die and package. Participating in design reviews across the global team. Engaging in package design, including interposer and RDL design. Collaborating closely with design teams in Vietnam, USA, Canada, and other countries to ensure the success of the whole product. Joining research programs to implement new ideas for future products and flows. Leading a layout team to complete a full design block. Mentoring junior layout engineers or interns. ### The Impact You Will Have Driving the development of high-performance Analog IPs that power cutting-edge technologies. Enhancing the layout design process for improved efficiency and quality. Ensuring the robustness and reliability of our designs through meticulous verification processes. Contributing to the integration of complex layouts into top-level designs. Fostering collaboration and knowledge sharing across global teams. Mentoring and developing the next generation of layout engineers. ### What You’ll Need BS in Electronics Engineering, Electromechanics, Telecommunications. 5+ years of experience in custom layout. ### Proficiency with layout entry tools Cadence, Synopsys. ### Experience with layout verification tools Mentor Calibre, Synopsys ICV. Understanding of basic semiconductor fabrication processes and MOSFET fundamentals. Knowledge of high-speed layout techniques, ESD, Latchup, Antenna, EMIR. Experience mentoring/leading junior layout engineers. Ability to write layout review presentations and layout verification reports. Good English communication skills. ### Who You Are You are a strong team player, self-motivated, humble, honest, and willing to learn. Your collaborative nature and excellent communication skills enable you to work effectively with colleagues across the globe. You are detail-oriented, have a passion for technology, and are committed to delivering high-quality work. Your leadership and mentoring abilities make you a valuable asset to any team. ### The Team You’ll Be A Part Of You will join a dynamic and innovative team focused on developing high-performance Analog IPs. Our team collaborates closely with colleagues in Vietnam, USA, Canada, and other countries to ensure the success of our products. We value teamwork, knowledge sharing, and continuous improvement, and we are committed to fostering a supportive and inclusive work environment. ### Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. ## At a glance - Posted by the employer: Oct 15, 2026 - First seen by OpenNash: Oct 18, 2026 - Last checked: Oct 18, 2026 - Listed for: 3 days - Location: Hanoi, Viet Nam - Pay: {'@type': 'MonetaryAmount', 'currency': '', 'value': {'@type': 'QuantitativeValue', 'unitText': ''}}[Apply on Synopsys’s careers site →](https://careers.synopsys.com/job/hanoi/analog-layout-design-staff-engineer-in-da-nang-ha-noi/44408/101981588832) ## More jobs at Synopsys ### [ASIC Design / Verification, Manager-Sr Manager](https://jobs.opennash.com/companies/synopsys/jobs/de52c027f8e62aaeb0a3/) Hsinchu, Taiwan ### [ASIC Design /Verification Engineer, Sr Staff](https://jobs.opennash.com/companies/synopsys/jobs/026bdf933bed4a29d3ac/) Tokyo, Japan ### [ASIC Design Engineer, Sr. Staff-18490](https://jobs.opennash.com/companies/synopsys/jobs/0ea4ef8bc9950f244a31/) United States Off-site ### [ASIC Design Verification Engineer, Staff - Principal](https://jobs.opennash.com/companies/synopsys/jobs/ba35fce3a3bcb461af94/) Hsinchu, Taiwan ### [ASIC Design Verification, Architect](https://jobs.opennash.com/companies/synopsys/jobs/8650de9c25c2c73105c4/) Hsinchu, Taiwan ## Similar jobs at other companies ### [Staff Engineer Analog Layout](https://jobs.opennash.com/companies/infineon-technologies/jobs/dae39b856c85418d4dfc/) Infineon Technologies · Hanoi ### [Staff Engineer Analog Layout](https://jobs.opennash.com/companies/infineon-technologies/jobs/a6206d71c9dd6693d96d/) Infineon Technologies · Penang ### [Staff Engineer, Analog Design](https://jobs.opennash.com/companies/renesas-electronics/jobs/10887787d51748b3d927/) Renesas Electronics · Bengaluru, KA, India ### [Staff Analog IC Design Engineer (ADC)](https://jobs.opennash.com/companies/qualcomm/jobs/eb6fb3301eee89692723/) Qualcomm · Singapore, Central Singapore ### [Staff Analog Layout Design Engineer](https://jobs.opennash.com/companies/advanced-micro-devices-amd/jobs/d49aefee80559e80ea98/) Advanced Micro Devices (AMD) · Penang, Malaysia [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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